diff mbox series

[v11,18/20] target/arm: Use vector infrastructure for aa64 orr/bic immediate

Message ID 20180126045742.5487-19-richard.henderson@linaro.org
State Superseded
Headers show
Series tcg: generic vector operations | expand

Commit Message

Richard Henderson Jan. 26, 2018, 4:57 a.m. UTC 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/translate-a64.c | 28 +++++-----------------------
 1 file changed, 5 insertions(+), 23 deletions(-)

-- 
2.14.3

Comments

Alex Bennée Feb. 6, 2018, 11:13 a.m. UTC | #1 
Richard Henderson <richard.henderson@linaro.org> writes:

> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


> ---

>  target/arm/translate-a64.c | 28 +++++-----------------------

>  1 file changed, 5 insertions(+), 23 deletions(-)

>

> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

> index 64a2c2df59..d688a699be 100644

> --- a/target/arm/translate-a64.c

> +++ b/target/arm/translate-a64.c

> @@ -6180,7 +6180,6 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)

>      bool is_neg = extract32(insn, 29, 1);

>      bool is_q = extract32(insn, 30, 1);

>      uint64_t imm = 0;

> -    int i;

>

>      if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {

>          unallocated_encoding(s);

> @@ -6266,29 +6265,12 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)

>          tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8,

>                              vec_full_reg_size(s), imm);

>      } else {

> -        TCGv_i64 tcg_imm = tcg_const_i64(imm);

> -        TCGv_i64 tcg_rd = new_tmp_a64(s);

> -

> -        for (i = 0; i < 2; i++) {

> -            int foffs = vec_reg_offset(s, rd, i, MO_64);

> -

> -            if (i == 1 && !is_q) {

> -                /* non-quad ops clear high half of vector */

> -                tcg_gen_movi_i64(tcg_rd, 0);

> -            } else {

> -                tcg_gen_ld_i64(tcg_rd, cpu_env, foffs);

> -                if (is_neg) {

> -                    /* AND (BIC) */

> -                    tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm);

> -                } else {

> -                    /* ORR */

> -                    tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm);

> -                }

> -            }

> -            tcg_gen_st_i64(tcg_rd, cpu_env, foffs);

> +        /* ORR or BIC, with BIC negation to AND handled above.  */

> +        if (is_neg) {

> +            gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_64);

> +        } else {

> +            gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_64);

>          }

> -

> -        tcg_temp_free_i64(tcg_imm);

>      }

>  }



--
Alex Bennée
diff mbox series

Patch

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 64a2c2df59..d688a699be 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6180,7 +6180,6 @@  static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
     bool is_neg = extract32(insn, 29, 1);
     bool is_q = extract32(insn, 30, 1);
     uint64_t imm = 0;
-    int i;
 
     if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
         unallocated_encoding(s);
@@ -6266,29 +6265,12 @@  static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8,
                             vec_full_reg_size(s), imm);
     } else {
-        TCGv_i64 tcg_imm = tcg_const_i64(imm);
-        TCGv_i64 tcg_rd = new_tmp_a64(s);
-
-        for (i = 0; i < 2; i++) {
-            int foffs = vec_reg_offset(s, rd, i, MO_64);
-
-            if (i == 1 && !is_q) {
-                /* non-quad ops clear high half of vector */
-                tcg_gen_movi_i64(tcg_rd, 0);
-            } else {
-                tcg_gen_ld_i64(tcg_rd, cpu_env, foffs);
-                if (is_neg) {
-                    /* AND (BIC) */
-                    tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm);
-                } else {
-                    /* ORR */
-                    tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm);
-                }
-            }
-            tcg_gen_st_i64(tcg_rd, cpu_env, foffs);
+        /* ORR or BIC, with BIC negation to AND handled above.  */
+        if (is_neg) {
+            gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_64);
+        } else {
+            gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_64);
         }
-
-        tcg_temp_free_i64(tcg_imm);
     }
 }