| Message ID | 1515168960-18960-7-git-send-email-jun.nie@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [[PATCH,v2] 6/8] sunxi: usb_phy: Clear PHYCTL register before writing | expand |
On Fri, Jan 5, 2018 at 9:45 PM, Jun Nie <jun.nie@linaro.org> wrote: > PHYCTL register offset at 0x10 need to be cleared before it's > written. Ported from below Linux patch. > d699c1d phy: sun4i-usb: change PHYCTL register clearing code > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > --- > arch/arm/mach-sunxi/usb_phy.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c > index 2f1cad1..bcf5f15 100644 > --- a/arch/arm/mach-sunxi/usb_phy.c > +++ b/arch/arm/mach-sunxi/usb_phy.c > @@ -156,9 +156,15 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, > static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) > { > #if defined CONFIG_MACH_SUNXI_H3_H5 > - if (phy->id == 0) > + if (phy->id == 0) { > +#ifdef CONFIG_USB_MUSB_GADGET > + setbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); > + writel(0, SUNXI_USB0_BASE + SUNXI_USB_CSR); This can't dependent on mode.
On Sun, Jan 28, 2018 at 2:43 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: > On Fri, Jan 5, 2018 at 9:45 PM, Jun Nie <jun.nie@linaro.org> wrote: >> PHYCTL register offset at 0x10 need to be cleared before it's >> written. Ported from below Linux patch. >> d699c1d phy: sun4i-usb: change PHYCTL register clearing code >> >> Signed-off-by: Jun Nie <jun.nie@linaro.org> >> --- >> arch/arm/mach-sunxi/usb_phy.c | 8 +++++++- >> 1 file changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c >> index 2f1cad1..bcf5f15 100644 >> --- a/arch/arm/mach-sunxi/usb_phy.c >> +++ b/arch/arm/mach-sunxi/usb_phy.c >> @@ -156,9 +156,15 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, >> static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) >> { >> #if defined CONFIG_MACH_SUNXI_H3_H5 >> - if (phy->id == 0) >> + if (phy->id == 0) { >> +#ifdef CONFIG_USB_MUSB_GADGET >> + setbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); >> + writel(0, SUNXI_USB0_BASE + SUNXI_USB_CSR); > > This can't dependent on mode. infact clear phyctl was already added in usb_phy_write, you can reuse the same for H3_H5
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 2f1cad1..bcf5f15 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -156,9 +156,15 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) { #if defined CONFIG_MACH_SUNXI_H3_H5 - if (phy->id == 0) + if (phy->id == 0) { +#ifdef CONFIG_USB_MUSB_GADGET + setbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); + writel(0, SUNXI_USB0_BASE + SUNXI_USB_CSR); +#else clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); #endif + } +#endif clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); } #elif defined CONFIG_MACH_SUN8I_A83T
PHYCTL register offset at 0x10 need to be cleared before it's written. Ported from below Linux patch. d699c1d phy: sun4i-usb: change PHYCTL register clearing code Signed-off-by: Jun Nie <jun.nie@linaro.org> --- arch/arm/mach-sunxi/usb_phy.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)