Message ID | 8d8cb956e0a679fcf0a8e24f1b2f34e038cdd48e.1511212753.git.riku.voipio@linaro.org |
---|---|
State | Accepted |
Commit | 8d8cb956e0a679fcf0a8e24f1b2f34e038cdd48e |
Headers | show
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[91.157.170.157]) by smtp.gmail.com with ESMTPSA id v63sm1645409lje.39.2017.11.20.13.22.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Nov 2017 13:22:03 -0800 (PST) From: riku.voipio@linaro.org To: qemu-devel@nongnu.org Date: Mon, 20 Nov 2017 23:21:41 +0200 Message-Id: <8d8cb956e0a679fcf0a8e24f1b2f34e038cdd48e.1511212753.git.riku.voipio@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <cover.1511212753.git.riku.voipio@linaro.org> References: <cover.1511212753.git.riku.voipio@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PULL 13/15] linux-user/sparc: Put address for data faults where linux-user expects it X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: Peter Maydell <peter.maydell@linaro.org> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org> |
Series |
late linux-user fixes for 2.11
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expand
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diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 126ea5e3ee..d5b6c1e48c 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -30,10 +30,18 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + if (rw & 2) { cs->exception_index = TT_TFAULT; } else { cs->exception_index = TT_DFAULT; +#ifdef TARGET_SPARC64 + env->dmmu.mmuregs[4] = address; +#else + env->mmuregs[4] = address; +#endif } return 1; }