diff mbox series

ahci: Add support for Cavium's fifth generation SATA controller

Message ID 1507700271-12910-1-git-send-email-mohun106@gmail.com
State New
Headers show
Series ahci: Add support for Cavium's fifth generation SATA controller | expand

Commit Message

Radha Mohan Chintakuntla Oct. 11, 2017, 5:37 a.m. UTC 
From: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>


This patch adds support for Cavium's fifth generation SATA controller.
It is an on-chip controller and complies with AHCI 1.3.1. As the
controller uses 64-bit addresses it cannot use the standard AHCI BAR5
and so uses BAR4.

Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>

---
 drivers/ata/ahci.c |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)

-- 
1.7.1

Comments

Tejun Heo Oct. 11, 2017, 2:09 p.m. UTC | #1 
On Tue, Oct 10, 2017 at 10:37:51PM -0700, Radha Mohan Chintakuntla wrote:
> From: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>

> 

> This patch adds support for Cavium's fifth generation SATA controller.

> It is an on-chip controller and complies with AHCI 1.3.1. As the

> controller uses 64-bit addresses it cannot use the standard AHCI BAR5

> and so uses BAR4.

> 

> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>


Applied to libata/for-4.15.

Thanks.

-- 
tejun
'Christoph Hellwig' Oct. 17, 2017, 6:58 a.m. UTC | #2 
On Tue, Oct 10, 2017 at 10:37:51PM -0700, Radha Mohan Chintakuntla wrote:
> From: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>

> 

> This patch adds support for Cavium's fifth generation SATA controller.

> It is an on-chip controller and complies with AHCI 1.3.1. As the

> controller uses 64-bit addresses it cannot use the standard AHCI BAR5

> and so uses BAR4.


Looks like it isn't actually AHCI 1.3.1 compliant after all then :)
Jon Masters Oct. 31, 2017, 10:05 a.m. UTC | #3 
On 10/17/2017 02:58 AM, Christoph Hellwig wrote:
> On Tue, Oct 10, 2017 at 10:37:51PM -0700, Radha Mohan Chintakuntla wrote:

>> From: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>

>>

>> This patch adds support for Cavium's fifth generation SATA controller.

>> It is an on-chip controller and complies with AHCI 1.3.1. As the

>> controller uses 64-bit addresses it cannot use the standard AHCI BAR5

>> and so uses BAR4.

> 

> Looks like it isn't actually AHCI 1.3.1 compliant after all then :)


I've asked various folks to followup with Intel to see if the AHCI
specification can be fixed to handle the case in which a 64-bit ABAR is
required. That should be something they'd be interested in for x86 too.

Jon.
diff mbox series

Patch

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 9f78bb0..5443cb7 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -57,6 +57,7 @@  enum {
 	AHCI_PCI_BAR_STA2X11	= 0,
 	AHCI_PCI_BAR_CAVIUM	= 0,
 	AHCI_PCI_BAR_ENMOTUS	= 2,
+	AHCI_PCI_BAR_CAVIUM_GEN5	= 4,
 	AHCI_PCI_BAR_STANDARD	= 5,
 };
 
@@ -1570,8 +1571,12 @@  static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 		ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
 	else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
 		ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
-	else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
-		ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
+	else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
+		if (pdev->device == 0xa01c)
+			ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
+		if (pdev->device == 0xa084)
+			ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
+	}
 
 	/* acquire resources */
 	rc = pcim_enable_device(pdev);