diff mbox

spi/pl022: adopt pinctrl support

Message ID 1348057426-24898-1-git-send-email-linus.walleij@stericsson.com
State New
Headers show

Commit Message

Linus Walleij Sept. 19, 2012, 12:23 p.m. UTC 
From: Patrice Chotard <patrice.chotard@stericsson.com>

Amend the PL022 pin controller to optionally take a pin control
handle and set the state of the pins to "default" on boot and
runtime resume, and to "sleep" at runtime suspend. This way we
will dynamically save power on the SPI busses, for example some
electronic designs may be able to ground the pins when unused
instead of pull-up. Some pin controllers may want to set the
pins as wake-up sources when sleeping.

Effect on platforms using the PL022 driver:

- If the platform does not use pin control - no semantic effect,
  the pinctrl stubs will kick in and resolve the situation.

- Platforms using this driver and have pin control but no
  function defined for the PL022 need to either supply a
  "default" function in their map or enable pinctrl dummies
  so the driver is satisfied.

- Platforms using this driver with hogs for setting up the PL022
  pin control - stop using hogs to take the pl022 pin control
  handle, let the driver handle this.

I'be looked at some platforms that may be affected:

- SPEAr: appears to define the proper functions in their device
  trees and not hogging them, so things should be smooth, the
  driver will simply start to take its pins.

- Ux500: the proper function is defined and will be taken properly
  by the driver. New sleep states introduced by a separate patch to
  ux500 but no regression, since the default state is sufficient.

- U300: old hog deleted as part of this patch.

- LPC32xx: does not appear to be using pinctrl.

- ARM Integrator IMPD1, RealView & Versatile: does not use pinctrl.

Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Roland Stigge <stigge@antcom.de>
Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Vinit Kamalaksha Shenoy <vinit.shenoy@st.com>
Cc: Viresh Kumar <viresh.kumar@arm.com>
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/mach-u300/core.c |  3 ---
 drivers/spi/spi-pl022.c   | 46 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+), 3 deletions(-)
diff mbox

Patch

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 03acf18..281292e 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1605,9 +1605,6 @@  static struct u300_mux_hog u300_mux_hogs[] = {
 		.dev = &uart0_device.dev,
 	},
 	{
-		.dev = &pl022_device.dev,
-	},
-	{
 		.dev = &mmcsd_device.dev,
 	},
 };
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index e43b610..423513c 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -42,6 +42,7 @@ 
 #include <linux/pm_runtime.h>
 #include <linux/gpio.h>
 #include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
 
 /*
  * This macro is used to define some register default values.
@@ -367,6 +368,10 @@  struct pl022 {
 	resource_size_t			phybase;
 	void __iomem			*virtbase;
 	struct clk			*clk;
+	/* Two optional pin states - default & sleep */
+	struct pinctrl			*pinctrl;
+	struct pinctrl_state		*pins_default;
+	struct pinctrl_state		*pins_sleep;
 	struct spi_master		*master;
 	struct pl022_ssp_controller	*master_info;
 	/* Message per-transfer pump */
@@ -2068,6 +2073,28 @@  pl022_probe(struct amba_device *adev, const struct amba_id *id)
 	pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int),
 					  GFP_KERNEL);
 
+	pl022->pinctrl = devm_pinctrl_get(dev);
+	if (IS_ERR(pl022->pinctrl)) {
+		status = PTR_ERR(pl022->pinctrl);
+		goto err_no_pinctrl;
+	}
+
+	pl022->pins_default = pinctrl_lookup_state(pl022->pinctrl,
+						 PINCTRL_STATE_DEFAULT);
+	/* enable pins to be muxed in and configured */
+	if (!IS_ERR(pl022->pins_default)) {
+		status = pinctrl_select_state(pl022->pinctrl,
+				pl022->pins_default);
+		if (status)
+			dev_err(dev, "could not set default pins\n");
+	} else
+		dev_err(dev, "could not get default pinstate\n");
+
+	pl022->pins_sleep = pinctrl_lookup_state(pl022->pinctrl,
+					       PINCTRL_STATE_SLEEP);
+	if (IS_ERR(pl022->pins_sleep))
+		dev_dbg(dev, "could not get sleep pinstate\n");
+
 	/*
 	 * Bus Number Which has been Assigned to this SSP controller
 	 * on this board
@@ -2217,6 +2244,7 @@  pl022_probe(struct amba_device *adev, const struct amba_id *id)
 	amba_release_regions(adev);
  err_no_ioregion:
  err_no_gpio:
+ err_no_pinctrl:
 	spi_master_put(master);
  err_no_master:
  err_no_pdata:
@@ -2290,15 +2318,33 @@  static int pl022_resume(struct device *dev)
 static int pl022_runtime_suspend(struct device *dev)
 {
 	struct pl022 *pl022 = dev_get_drvdata(dev);
+	int status = 0;
 
 	clk_disable(pl022->clk);
 
+	/* Optionally let pins go into sleep states */
+	if (!IS_ERR(pl022->pins_sleep)) {
+		status = pinctrl_select_state(pl022->pinctrl,
+				pl022->pins_sleep);
+		if (status)
+			dev_err(dev, "could not set pins to sleep state\n");
+	}
+
 	return 0;
 }
 
 static int pl022_runtime_resume(struct device *dev)
 {
 	struct pl022 *pl022 = dev_get_drvdata(dev);
+	int status = 0;
+
+	/* Optionaly enable pins to be muxed in and configured */
+	if (!IS_ERR(pl022->pins_default)) {
+		status = pinctrl_select_state(pl022->pinctrl,
+				pl022->pins_default);
+		if (status)
+			dev_err(dev, "could not set default pins\n");
+	}
 
 	clk_enable(pl022->clk);