| Message ID | 20170810072346.32299-2-suzuki.katsuhiro@socionext.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/2] clk: uniphier: add audio system clock | expand |
2017-08-10 16:23 GMT+09:00 Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>: > Add a clock for video input subsystem (EXIV) on > UniPhier LD11/LD20 SoCs. > > Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> -- Best Regards Masahiro Yamada
On 08/10, Katsuhiro Suzuki wrote: > Add a clock for video input subsystem (EXIV) on > UniPhier LD11/LD20 SoCs. > > Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> > --- Applied to clk-next with some conflict resolving, please check. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Hello Stephen, > Applied to clk-next with some conflict resolving, please check. No problem. Thank you for applying! Regards, -- Katsuhiro Suzuki > -----Original Message----- > From: Stephen Boyd [mailto:sboyd@codeaurora.org] > Sent: Friday, September 1, 2017 10:42 AM > To: Suzuki, Katsuhiro/鈴木 勝博 <suzuki.katsuhiro@socionext.com> > Cc: Michael Turquette <mturquette@baylibre.com>; Yamada, Masahiro/山田 真弘 > <yamada.masahiro@socionext.com>; linux-clk@vger.kernel.org; Masami Hiramatsu <masami.hiramatsu@linaro.org>; > Jassi Brar <jaswinder.singh@linaro.org>; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 2/2] clk: uniphier: add video input subsystem clock > > On 08/10, Katsuhiro Suzuki wrote: > > Add a clock for video input subsystem (EXIV) on UniPhier LD11/LD20 > > SoCs. > > > > Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> > > --- > > Applied to clk-next with some conflict resolving, please check. > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 7c4528d0fb6e..c60aa586fea7 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -65,6 +65,10 @@ UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \ UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1) +#define UNIPHIER_LD11_SYS_CLK_EXIV(idx) \ + UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \ + UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2) + const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */ UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */ @@ -168,6 +172,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25), UNIPHIER_LD11_SYS_CLK_AIO(40), UNIPHIER_LD11_SYS_CLK_EVEA(41), + UNIPHIER_LD11_SYS_CLK_EXIV(42), /* CPU gears */ UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8), @@ -206,6 +211,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13), UNIPHIER_LD11_SYS_CLK_AIO(40), UNIPHIER_LD11_SYS_CLK_EVEA(41), + UNIPHIER_LD11_SYS_CLK_EXIV(42), /* CPU gears */ UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
Add a clock for video input subsystem (EXIV) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> --- drivers/clk/uniphier/clk-uniphier-sys.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.13.2