diff mbox series

[v5,1/2] ACPI/IORT: Add ITS address regions reservation helper

Message ID 20170801104913.71912-2-shameerali.kolothum.thodi@huawei.com
State Superseded
Headers show
Series iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) | expand

Commit Message

Shameerali Kolothum Thodi Aug. 1, 2017, 10:49 a.m. UTC 
On some platforms ITS address regions have to be excluded from normal
IOVA allocation in that they are detected and decoded in a HW specific
way by system components and so they cannot be considered normal IOVA
address space.

Add an helper function that retrieves ITS address regions through IORT
device <-> ITS mappings and reserves it so that these regions will not
be translated by IOMMU and will be excluded from IOVA allocations.

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

[lorenzo.pieralisi@arm.com: updated commit log/added comments]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

---
 drivers/acpi/arm64/iort.c        | 95 ++++++++++++++++++++++++++++++++++++++--
 drivers/irqchip/irq-gic-v3-its.c |  3 +-
 include/linux/acpi_iort.h        |  7 ++-
 3 files changed, 100 insertions(+), 5 deletions(-)

-- 
1.9.1


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Comments

Robin Murphy Aug. 4, 2017, 4:57 p.m. UTC | #1 
On 01/08/17 11:49, Shameer Kolothum wrote:
> On some platforms ITS address regions have to be excluded from normal

> IOVA allocation in that they are detected and decoded in a HW specific

> way by system components and so they cannot be considered normal IOVA

> address space.

> 

> Add an helper function that retrieves ITS address regions through IORT

> device <-> ITS mappings and reserves it so that these regions will not

> be translated by IOMMU and will be excluded from IOVA allocations.


I've just realised that we no longer seem to have a check that ensures
the regions are only reserved on platforms that need it - if not, then
we're going to break everything else that does have an ITS behind SMMU
translation as expected.

It feels like IORT should know enough to be able to make that decision
internally, but if not (or if it would be hideous to do so), then I
guess my idea for patch #2 was a bust and we probably do need to go back
to calling directly from the SMMU driver based on the SMMU model.

Robin.

> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

> [lorenzo.pieralisi@arm.com: updated commit log/added comments]

> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

> ---

>  drivers/acpi/arm64/iort.c        | 95 ++++++++++++++++++++++++++++++++++++++--

>  drivers/irqchip/irq-gic-v3-its.c |  3 +-

>  include/linux/acpi_iort.h        |  7 ++-

>  3 files changed, 100 insertions(+), 5 deletions(-)

> 

> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c

> index a3215ee..86b5a51 100644

> --- a/drivers/acpi/arm64/iort.c

> +++ b/drivers/acpi/arm64/iort.c

> @@ -39,6 +39,7 @@

>  struct iort_its_msi_chip {

>  	struct list_head	list;

>  	struct fwnode_handle	*fw_node;

> +	phys_addr_t		base_addr;

>  	u32			translation_id;

>  };

>  

> @@ -136,14 +137,16 @@ typedef acpi_status (*iort_find_node_callback)

>  static DEFINE_SPINLOCK(iort_msi_chip_lock);

>  

>  /**

> - * iort_register_domain_token() - register domain token and related ITS ID

> - * to the list from where we can get it back later on.

> + * iort_register_domain_token() - register domain token along with related

> + * ITS ID and base address to the list from where we can get it back later on.

>   * @trans_id: ITS ID.

> + * @base: ITS base address.

>   * @fw_node: Domain token.

>   *

>   * Returns: 0 on success, -ENOMEM if no memory when allocating list element

>   */

> -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node)

> +int iort_register_domain_token(int trans_id, phys_addr_t base,

> +			       struct fwnode_handle *fw_node)

>  {

>  	struct iort_its_msi_chip *its_msi_chip;

>  

> @@ -153,6 +156,7 @@ int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node)

>  

>  	its_msi_chip->fw_node = fw_node;

>  	its_msi_chip->translation_id = trans_id;

> +	its_msi_chip->base_addr = base;

>  

>  	spin_lock(&iort_msi_chip_lock);

>  	list_add(&its_msi_chip->list, &iort_msi_chip_list);

> @@ -481,6 +485,24 @@ int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id)

>  	return -ENODEV;

>  }

>  

> +static int __maybe_unused iort_find_its_base(u32 its_id, phys_addr_t *base)

> +{

> +	struct iort_its_msi_chip *its_msi_chip;

> +	bool match = false;

> +

> +	spin_lock(&iort_msi_chip_lock);

> +	list_for_each_entry(its_msi_chip, &iort_msi_chip_list, list) {

> +		if (its_msi_chip->translation_id == its_id) {

> +			*base = its_msi_chip->base_addr;

> +			match = true;

> +			break;

> +		}

> +	}

> +	spin_unlock(&iort_msi_chip_lock);

> +

> +	return match ? 0 : -ENODEV;

> +}

> +

>  /**

>   * iort_dev_find_its_id() - Find the ITS identifier for a device

>   * @dev: The device.

> @@ -639,6 +661,71 @@ int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev)

>  

>  	return err;

>  }

> +

> +/**

> + * iort_iommu_its_get_resv_regions - Reserved region driver helper

> + * @dev: Device from iommu_get_resv_regions()

> + * @list: Reserved region list from iommu_get_resv_regions()

> + *

> + * Returns: Number of reserved regions on success(0 if no associated ITS),

> + *          appropriate error value otherwise.

> + */

> +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head)

> +{

> +	struct acpi_iort_its_group *its;

> +	struct acpi_iort_node *node, *its_node = NULL;

> +	int i, resv = 0;

> +

> +	node = iort_find_dev_node(dev);

> +	if (!node)

> +		return -ENODEV;

> +

> +	/*

> +	 * Current logic to reserve ITS regions relies on HW topologies

> +	 * where a given PCI or named component maps its IDs to only one

> +	 * ITS group; if a PCI or named component can map its IDs to

> +	 * different ITS groups through IORT mappings this function has

> +	 * to be reworked to ensure we reserve regions for all ITS groups

> +	 * a given PCI or named component may map IDs to.

> +	 */

> +	if (dev_is_pci(dev)) {

> +		u32 rid;

> +

> +		pci_for_each_dma_alias(to_pci_dev(dev), __get_pci_rid, &rid);

> +		its_node = iort_node_map_id(node, rid, NULL, IORT_MSI_TYPE);

> +	} else {

> +		for (i = 0; i < node->mapping_count; i++) {

> +			its_node = iort_node_map_platform_id(node, NULL,

> +							 IORT_MSI_TYPE, i);

> +			if (its_node)

> +				break;

> +		}

> +	}

> +

> +	if (!its_node)

> +		return 0;

> +

> +	/* Move to ITS specific data */

> +	its = (struct acpi_iort_its_group *)its_node->node_data;

> +

> +	for (i = 0; i < its->its_count; i++) {

> +		phys_addr_t base;

> +

> +		if (!iort_find_its_base(its->identifiers[i], &base)) {

> +			int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;

> +			struct iommu_resv_region *region;

> +

> +			region = iommu_alloc_resv_region(base, SZ_128K, prot,

> +							 IOMMU_RESV_MSI);

> +			if (region) {

> +				list_add_tail(&region->list, head);

> +				resv++;

> +			}

> +		}

> +	}

> +

> +	return (resv == its->its_count) ? resv : -ENODEV;

> +}

>  #else

>  static inline

>  const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec)

> @@ -646,6 +733,8 @@ const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec)

>  static inline

>  int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev)

>  { return 0; }

> +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head)

> +{ return -ENODEV; }

>  #endif

>  

>  static const struct iommu_ops *iort_iommu_xlate(struct device *dev,

> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c

> index 6893287..77322b3 100644

> --- a/drivers/irqchip/irq-gic-v3-its.c

> +++ b/drivers/irqchip/irq-gic-v3-its.c

> @@ -1928,7 +1928,8 @@ static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header,

>  		return -ENOMEM;

>  	}

>  

> -	err = iort_register_domain_token(its_entry->translation_id, dom_handle);

> +	err = iort_register_domain_token(its_entry->translation_id, res.start,

> +					 dom_handle);

>  	if (err) {

>  		pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",

>  		       &res.start, its_entry->translation_id);

> diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h

> index 8379d40..d7ed49c 100644

> --- a/include/linux/acpi_iort.h

> +++ b/include/linux/acpi_iort.h

> @@ -26,7 +26,8 @@

>  #define IORT_IRQ_MASK(irq)		(irq & 0xffffffffULL)

>  #define IORT_IRQ_TRIGGER_MASK(irq)	((irq >> 32) & 0xffffffffULL)

>  

> -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node);

> +int iort_register_domain_token(int trans_id, phys_addr_t base,

> +			       struct fwnode_handle *fw_node);

>  void iort_deregister_domain_token(int trans_id);

>  struct fwnode_handle *iort_find_domain_token(int trans_id);

>  #ifdef CONFIG_ACPI_IORT

> @@ -38,6 +39,7 @@

>  /* IOMMU interface */

>  void iort_set_dma_mask(struct device *dev);

>  const struct iommu_ops *iort_iommu_configure(struct device *dev);

> +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head);

>  #else

>  static inline void acpi_iort_init(void) { }

>  static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id)

> @@ -51,6 +53,9 @@ static inline void iort_set_dma_mask(struct device *dev) { }

>  static inline

>  const struct iommu_ops *iort_iommu_configure(struct device *dev)

>  { return NULL; }

> +static inline

> +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head)

> +{ return -ENODEV; }

>  #endif

>  

>  #endif /* __ACPI_IORT_H__ */

> 


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Shameerali Kolothum Thodi Aug. 7, 2017, 8:21 a.m. UTC | #2 
> -----Original Message-----

> From: Robin Murphy [mailto:robin.murphy@arm.com]

> Sent: Friday, August 04, 2017 5:57 PM

> To: Shameerali Kolothum Thodi; lorenzo.pieralisi@arm.com;

> marc.zyngier@arm.com; sudeep.holla@arm.com; will.deacon@arm.com;

> hanjun.guo@linaro.org

> Cc: Gabriele Paoloni; John Garry; iommu@lists.linux-foundation.org; linux-

> arm-kernel@lists.infradead.org; linux-acpi@vger.kernel.org;

> devel@acpica.org; Linuxarm; Wangzhou (B); Guohanjun (Hanjun Guo)

> Subject: Re: [PATCH v5 1/2] ACPI/IORT: Add ITS address regions reservation

> helper

> 

> On 01/08/17 11:49, Shameer Kolothum wrote:

> > On some platforms ITS address regions have to be excluded from normal

> > IOVA allocation in that they are detected and decoded in a HW specific

> > way by system components and so they cannot be considered normal

> IOVA

> > address space.

> >

> > Add an helper function that retrieves ITS address regions through IORT

> > device <-> ITS mappings and reserves it so that these regions will not

> > be translated by IOMMU and will be excluded from IOVA allocations.

> 

> I've just realised that we no longer seem to have a check that ensures

> the regions are only reserved on platforms that need it - if not, then

> we're going to break everything else that does have an ITS behind SMMU

> translation as expected.


Right. I had this doubt, but then my thinking was that we will have the SW_MSI
regions for those and will end up  using that. But that doesn’t seems
to be the case now.

> It feels like IORT should know enough to be able to make that decision

> internally, but if not (or if it would be hideous to do so), then I

> guess my idea for patch #2 was a bust and we probably do need to go back

> to calling directly from the SMMU driver based on the SMMU model.


It might be possible to do that check inside iort code, but then we have to find
the  smmu node first and check the model number. I think it will be more
cleaner if SMMU driver makes that check and call the
iommu_dma_get_msi_resv_regions().

If you are Ok with that I will quickly rework and send out the next version.

Thanks,
Shameer
Lorenzo Pieralisi Aug. 7, 2017, 5:09 p.m. UTC | #3 
On Mon, Aug 07, 2017 at 08:21:40AM +0000, Shameerali Kolothum Thodi wrote:
> 

> 

> > -----Original Message-----

> > From: Robin Murphy [mailto:robin.murphy@arm.com]

> > Sent: Friday, August 04, 2017 5:57 PM

> > To: Shameerali Kolothum Thodi; lorenzo.pieralisi@arm.com;

> > marc.zyngier@arm.com; sudeep.holla@arm.com; will.deacon@arm.com;

> > hanjun.guo@linaro.org

> > Cc: Gabriele Paoloni; John Garry; iommu@lists.linux-foundation.org; linux-

> > arm-kernel@lists.infradead.org; linux-acpi@vger.kernel.org;

> > devel@acpica.org; Linuxarm; Wangzhou (B); Guohanjun (Hanjun Guo)

> > Subject: Re: [PATCH v5 1/2] ACPI/IORT: Add ITS address regions reservation

> > helper

> > 

> > On 01/08/17 11:49, Shameer Kolothum wrote:

> > > On some platforms ITS address regions have to be excluded from normal

> > > IOVA allocation in that they are detected and decoded in a HW specific

> > > way by system components and so they cannot be considered normal

> > IOVA

> > > address space.

> > >

> > > Add an helper function that retrieves ITS address regions through IORT

> > > device <-> ITS mappings and reserves it so that these regions will not

> > > be translated by IOMMU and will be excluded from IOVA allocations.

> > 

> > I've just realised that we no longer seem to have a check that ensures

> > the regions are only reserved on platforms that need it - if not, then

> > we're going to break everything else that does have an ITS behind SMMU

> > translation as expected.

> 

> Right. I had this doubt, but then my thinking was that we will have the SW_MSI

> regions for those and will end up  using that. But that doesn’t seems

> to be the case now.

> 

> > It feels like IORT should know enough to be able to make that decision

> > internally, but if not (or if it would be hideous to do so), then I

> > guess my idea for patch #2 was a bust and we probably do need to go back

> > to calling directly from the SMMU driver based on the SMMU model.

> 

> It might be possible to do that check inside iort code, but then we have to find

> the  smmu node first and check the model number. I think it will be more

> cleaner if SMMU driver makes that check and call the

> iommu_dma_get_msi_resv_regions().


+1 on this one - we can do it in IORT but I think it is more logical
to have a flag in the SMMU driver (keeping the DT/ACPI fwnode switch in
generic IOMMU layer though).

Side note I: AFAICS iommu_dma_get_resv_regions() is only used on ARM, if
it is not patch 2 would break miserably on arches that do not select
IORT - you should rework the return code on !CONFIG_ACPI_IORT configs.

Side note II(nit): why not call the function iort_iommu_get_resv_regions() ?

Lorenzo

> If you are Ok with that I will quickly rework and send out the next version.

> 

> Thanks,

> Shameer

> 

> _______________________________________________

> linux-arm-kernel mailing list

> linux-arm-kernel@lists.infradead.org

> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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Shameerali Kolothum Thodi Aug. 8, 2017, 9:49 a.m. UTC | #4 
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diff mbox series

Patch

diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
index a3215ee..86b5a51 100644
--- a/drivers/acpi/arm64/iort.c
+++ b/drivers/acpi/arm64/iort.c
@@ -39,6 +39,7 @@ 
 struct iort_its_msi_chip {
 	struct list_head	list;
 	struct fwnode_handle	*fw_node;
+	phys_addr_t		base_addr;
 	u32			translation_id;
 };
 
@@ -136,14 +137,16 @@  typedef acpi_status (*iort_find_node_callback)
 static DEFINE_SPINLOCK(iort_msi_chip_lock);
 
 /**
- * iort_register_domain_token() - register domain token and related ITS ID
- * to the list from where we can get it back later on.
+ * iort_register_domain_token() - register domain token along with related
+ * ITS ID and base address to the list from where we can get it back later on.
  * @trans_id: ITS ID.
+ * @base: ITS base address.
  * @fw_node: Domain token.
  *
  * Returns: 0 on success, -ENOMEM if no memory when allocating list element
  */
-int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node)
+int iort_register_domain_token(int trans_id, phys_addr_t base,
+			       struct fwnode_handle *fw_node)
 {
 	struct iort_its_msi_chip *its_msi_chip;
 
@@ -153,6 +156,7 @@  int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node)
 
 	its_msi_chip->fw_node = fw_node;
 	its_msi_chip->translation_id = trans_id;
+	its_msi_chip->base_addr = base;
 
 	spin_lock(&iort_msi_chip_lock);
 	list_add(&its_msi_chip->list, &iort_msi_chip_list);
@@ -481,6 +485,24 @@  int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id)
 	return -ENODEV;
 }
 
+static int __maybe_unused iort_find_its_base(u32 its_id, phys_addr_t *base)
+{
+	struct iort_its_msi_chip *its_msi_chip;
+	bool match = false;
+
+	spin_lock(&iort_msi_chip_lock);
+	list_for_each_entry(its_msi_chip, &iort_msi_chip_list, list) {
+		if (its_msi_chip->translation_id == its_id) {
+			*base = its_msi_chip->base_addr;
+			match = true;
+			break;
+		}
+	}
+	spin_unlock(&iort_msi_chip_lock);
+
+	return match ? 0 : -ENODEV;
+}
+
 /**
  * iort_dev_find_its_id() - Find the ITS identifier for a device
  * @dev: The device.
@@ -639,6 +661,71 @@  int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev)
 
 	return err;
 }
+
+/**
+ * iort_iommu_its_get_resv_regions - Reserved region driver helper
+ * @dev: Device from iommu_get_resv_regions()
+ * @list: Reserved region list from iommu_get_resv_regions()
+ *
+ * Returns: Number of reserved regions on success(0 if no associated ITS),
+ *          appropriate error value otherwise.
+ */
+int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head)
+{
+	struct acpi_iort_its_group *its;
+	struct acpi_iort_node *node, *its_node = NULL;
+	int i, resv = 0;
+
+	node = iort_find_dev_node(dev);
+	if (!node)
+		return -ENODEV;
+
+	/*
+	 * Current logic to reserve ITS regions relies on HW topologies
+	 * where a given PCI or named component maps its IDs to only one
+	 * ITS group; if a PCI or named component can map its IDs to
+	 * different ITS groups through IORT mappings this function has
+	 * to be reworked to ensure we reserve regions for all ITS groups
+	 * a given PCI or named component may map IDs to.
+	 */
+	if (dev_is_pci(dev)) {
+		u32 rid;
+
+		pci_for_each_dma_alias(to_pci_dev(dev), __get_pci_rid, &rid);
+		its_node = iort_node_map_id(node, rid, NULL, IORT_MSI_TYPE);
+	} else {
+		for (i = 0; i < node->mapping_count; i++) {
+			its_node = iort_node_map_platform_id(node, NULL,
+							 IORT_MSI_TYPE, i);
+			if (its_node)
+				break;
+		}
+	}
+
+	if (!its_node)
+		return 0;
+
+	/* Move to ITS specific data */
+	its = (struct acpi_iort_its_group *)its_node->node_data;
+
+	for (i = 0; i < its->its_count; i++) {
+		phys_addr_t base;
+
+		if (!iort_find_its_base(its->identifiers[i], &base)) {
+			int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
+			struct iommu_resv_region *region;
+
+			region = iommu_alloc_resv_region(base, SZ_128K, prot,
+							 IOMMU_RESV_MSI);
+			if (region) {
+				list_add_tail(&region->list, head);
+				resv++;
+			}
+		}
+	}
+
+	return (resv == its->its_count) ? resv : -ENODEV;
+}
 #else
 static inline
 const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec)
@@ -646,6 +733,8 @@  const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec)
 static inline
 int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev)
 { return 0; }
+int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head)
+{ return -ENODEV; }
 #endif
 
 static const struct iommu_ops *iort_iommu_xlate(struct device *dev,
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 6893287..77322b3 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1928,7 +1928,8 @@  static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header,
 		return -ENOMEM;
 	}
 
-	err = iort_register_domain_token(its_entry->translation_id, dom_handle);
+	err = iort_register_domain_token(its_entry->translation_id, res.start,
+					 dom_handle);
 	if (err) {
 		pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
 		       &res.start, its_entry->translation_id);
diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h
index 8379d40..d7ed49c 100644
--- a/include/linux/acpi_iort.h
+++ b/include/linux/acpi_iort.h
@@ -26,7 +26,8 @@ 
 #define IORT_IRQ_MASK(irq)		(irq & 0xffffffffULL)
 #define IORT_IRQ_TRIGGER_MASK(irq)	((irq >> 32) & 0xffffffffULL)
 
-int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node);
+int iort_register_domain_token(int trans_id, phys_addr_t base,
+			       struct fwnode_handle *fw_node);
 void iort_deregister_domain_token(int trans_id);
 struct fwnode_handle *iort_find_domain_token(int trans_id);
 #ifdef CONFIG_ACPI_IORT
@@ -38,6 +39,7 @@ 
 /* IOMMU interface */
 void iort_set_dma_mask(struct device *dev);
 const struct iommu_ops *iort_iommu_configure(struct device *dev);
+int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head);
 #else
 static inline void acpi_iort_init(void) { }
 static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id)
@@ -51,6 +53,9 @@  static inline void iort_set_dma_mask(struct device *dev) { }
 static inline
 const struct iommu_ops *iort_iommu_configure(struct device *dev)
 { return NULL; }
+static inline
+int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head)
+{ return -ENODEV; }
 #endif
 
 #endif /* __ACPI_IORT_H__ */