| Message ID | 20170710192128.9048-6-alex.bennee@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm: fixes for eret, isb and DISAS_UPDATE handling | expand |
On 07/10/2017 09:21 AM, Alex Bennée wrote: > Previously DISAS_JUMP did ensure this but with the optimisation of > 8a6b28c7 (optimize indirect branches) we might not leave the loop. > This means if any pending interrupts are cleared by changing IRQ flags > we might never get around to servicing them. You usually notice this > by seeing the lookup_tb_ptr() helper gainfully chaining TBs together > while cpu->interrupt_request remains high and the exit_request has not > been set. > > This breaks amongst other things the OPTEE test suite which executes > an eret from the secure world after a non-secure world IRQ has gone > pending which then never gets serviced. > > Instead of using the previously implied semantics of DISAS_JUMP we use > DISAS_EXIT which will always exit the run-loop. > > Signed-off-by: Alex Bennée<alex.bennee@linaro.org> > CC: Etienne Carriere<etienne.carriere@linaro.org> > CC: Joakim Bech<joakim.bech@linaro.org> > CC: Peter Maydell<peter.maydell@linaro.org> > CC: Emilio G. Cota<cota@braap.org> > CC: Richard Henderson<rth@twiddle.net> > --- > target/arm/translate-a64.c | 3 ++- > target/arm/translate.c | 6 ++++-- > 2 files changed, 6 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson <rth@twiddle.net> As an aside, I presume we don't have support for armv7ve? I was expecting there to be an eret insn in the aa32 translator and had to dig up previous manuals to see when that insn was introduced. r~
On 10 July 2017 at 20:58, Richard Henderson <rth@twiddle.net> wrote: > As an aside, I presume we don't have support for armv7ve? I was expecting > there to be an eret insn in the aa32 translator and had to dig up previous > manuals to see when that insn was introduced. We don't yet fully support 32-bit EL2, no. We've been adding bits and pieces but still haven't filled it all in. Edgar might have a patch to add ARM A32 ERET to the decoder in the xilinx tree? thanks -- PMM
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ad46d84efb..48825f5722 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1789,7 +1789,8 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) return; } gen_helper_exception_return(cpu_env); - s->is_jmp = DISAS_JUMP; + /* Must exit loop to check un-masked IRQs */ + s->is_jmp = DISAS_EXIT; return; case 5: /* DRPS */ if (rn != 0x1f) { diff --git a/target/arm/translate.c b/target/arm/translate.c index 94aa4bbb4d..c67a4f90d4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4484,7 +4484,8 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr) */ gen_helper_cpsr_write_eret(cpu_env, cpsr); tcg_temp_free_i32(cpsr); - s->is_jmp = DISAS_JUMP; + /* Must exit loop to check un-masked IRQs */ + s->is_jmp = DISAS_EXIT; } /* Generate an old-style exception return. Marks pc as dead. */ @@ -9528,7 +9529,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) tmp = load_cpu_field(spsr); gen_helper_cpsr_write_eret(cpu_env, tmp); tcg_temp_free_i32(tmp); - s->is_jmp = DISAS_JUMP; + /* Must exit loop to check un-masked IRQs */ + s->is_jmp = DISAS_EXIT; } } break;
Previously DISAS_JUMP did ensure this but with the optimisation of 8a6b28c7 (optimize indirect branches) we might not leave the loop. This means if any pending interrupts are cleared by changing IRQ flags we might never get around to servicing them. You usually notice this by seeing the lookup_tb_ptr() helper gainfully chaining TBs together while cpu->interrupt_request remains high and the exit_request has not been set. This breaks amongst other things the OPTEE test suite which executes an eret from the secure world after a non-secure world IRQ has gone pending which then never gets serviced. Instead of using the previously implied semantics of DISAS_JUMP we use DISAS_EXIT which will always exit the run-loop. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> CC: Etienne Carriere <etienne.carriere@linaro.org> CC: Joakim Bech <joakim.bech@linaro.org> CC: Peter Maydell <peter.maydell@linaro.org> CC: Emilio G. Cota <cota@braap.org> CC: Richard Henderson <rth@twiddle.net> --- target/arm/translate-a64.c | 3 ++- target/arm/translate.c | 6 ++++-- 2 files changed, 6 insertions(+), 3 deletions(-) -- 2.13.0