@@ -1,32 +1,19 @@
/{
- gpu: mali@E82C0000 {
- compatible = "arm,malit6xx", "arm,mali-midgard";
- gpu_outstanding = <0x0>;
- reg = <0x0 0xE82C0000 0x0 0x4000>;
- interrupts = <0 258 4 0 259 4 0 260 4>;
- interrupt-names = "JOB", "MMU", "GPU";
- clocks = <&stub_clock HI3660_CLK_STUB_GPU>;
- operating-points = <
- /* <frequency> <voltage>*/
- 178000 650000
- 400000 700000
- 533000 800000
- 807000 900000
- 960000 1000000
- 1037000 1100000
- >;
- cooling-min-level = <5>;
- cooling-max-level = <0>;
- #cooling-cells = <2>; /* min followed by max */
-
- gpu_power_model: power_model {
- compatible = "arm,mali-simple-power-model";
- voltage = <700>;
- frequency = <400>;
- static-power = <112>;
- dynamic-power = <980>;
- ts = <48020 2120 (-50) 1>;
- thermal-zone = "cls0";
- };
- };
+ gpu: mali@E82C0000 {
+ compatible = "arm,malit6xx", "arm,mali-midgard";
+ #cooling-cells = <3>; /* min followed by max */
+ gpu_outstanding = <0x0>;
+ reg = <0x0 0xE82C0000 0x0 0x4000>;
+ interrupts = <0 258 4 0 259 4 0 260 4>;
+ interrupt-names = "JOB", "MMU", "GPU";
+ operating-points = <
+ /* <frequency> <voltage>*/
+ 178000 650000
+ 400000 700000
+ 533000 800000
+ 807000 900000
+ 960000 1000000
+ 1037000 1100000
+ >;
+ };
};
old mode 100644
new mode 100755
@@ -8,17 +8,18 @@
/dts-v1/;
#include "hi3660.dtsi"
+#include "hi3660-ion.dtsi"
#include "hikey960-pinctrl.dtsi"
#include "hi3660-gpu.dtsi"
+#include "hi3660-drm.dtsi"
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include "hi3660-drm.dtsi"
-#include "hi3660-ion.dtsi"
/ {
model = "HiKey960";
compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
+ hisi,boardid = <5 3 0 0>;
aliases {
mshc1 = &dwmmc1;
@@ -41,12 +42,13 @@
reg = <0x0 0x00400000 0x0 0xBFE00000>;
};
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
- fastboot_cma: fastboot-cma-mem {
+ fastboot_cma: fastboot-cma-mem {
reg = <0x0 0x16c00000 0x0 0x4000000>;
compatible = "shared-dma-pool";
hisi,cma-sec;
@@ -58,176 +60,179 @@
no-map;
};
- ramoops@32000000 {
- compatible = "ramoops";
- reg = <0x0 0x32000000 0x0 0x00100000>;
- record-size = <0x00020000>;
- console-size = <0x00020000>;
- ftrace-size = <0x00020000>;
+ ramoops_ram:pstore-mem{
+ reg = <0x0 0x20A00000 0x0 0x100000>;
};
lpmx-core {
- reg = <0x0 0x89b80000 0x0 0x100000>;
+ reg = <0x0 0x89280000 0x0 0x100000>;
no-map;
};
lpmcu {
- reg = <0x0 0x89c80000 0x0 0x40000>;
+ reg = <0x0 0x89380000 0x0 0x40000>;
no-map;
};
};
- reboot-mode-syscon@32100000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x0 0x32100000 0x0 0x00001000>;
-
- reboot-mode {
- compatible = "syscon-reboot-mode";
- offset = <0x0>;
-
- mode-normal = <0x77665501>;
- mode-bootloader = <0x77665500>;
- mode-recovery = <0x77665502>;
+ soc {
+ uart6: uart@fff32000 {
+ status = "ok";
};
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;
- power {
- wakeup-source;
- gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
- label = "GPIO Power";
- linux,code = <KEY_POWER>;
+ ufs: ufs@ff3b0000 {
+ reset-gpio = <&gpio18 1 0>;
+ //vcc-supply = <&ldo15>;
};
};
- leds {
- compatible = "gpio-leds";
-
- user_led1 {
- label = "user_led1";
- /* gpio_150_user_led1 */
- gpios = <&gpio18 6 0>;
- linux,default-trigger = "heartbeat";
- };
-
- user_led2 {
- label = "user_led2";
- /* gpio_151_user_led2 */
- gpios = <&gpio18 7 0>;
- linux,default-trigger = "mmc0";
- };
-
- user_led3 {
- label = "user_led3";
- /* gpio_189_user_led3 */
- gpios = <&gpio23 5 0>;
- default-state = "off";
- };
-
- user_led4 {
- label = "user_led4";
- /* gpio_190_user_led4 */
- gpios = <&gpio23 6 0>;
- linux,default-trigger = "cpu0";
- };
-
- wlan_active_led {
- label = "wifi_active";
- /* gpio_205_wifi_active */
- gpios = <&gpio25 5 0>;
- linux,default-trigger = "phy0tx";
- default-state = "off";
- };
+ smmu {
+ compatible = "hisi,hisi-smmu";
+ phy_pgd_base = <0x0 0x34A78000>;
+ };
- bt_active_led {
- label = "bt_active";
- gpios = <&gpio25 7 0>;
- /* gpio_207_user_led1 */
- linux,default-trigger = "hci0-power";
- default-state = "off";
- };
+ smmu_lpae{
+ compatible = "hisi,hisi-smmu-lpae";
+ status = "ok";
};
pmic: pmic@fff34000 {
- compatible = "hisilicon,hi6421v530-pmic";
+ compatible = "hisilicon,hi6421-pmic";
reg = <0x0 0xfff34000 0x0 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
regulators {
- ldo3: LDO3 { /* HDMI */
- regulator-name = "VOUT3_1V85";
+ ldo1: LDO1 {
+ regulator-compatible = "hi6421v530_ldo1";
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo3: LDO3 {
+ regulator-compatible = "hi6421v530_ldo3";
+ regulator-name = "LDO3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2200000>;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo4: LDO4 {
+ regulator-compatible = "hi6421v530_ldo4";
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
regulator-enable-ramp-delay = <120>;
};
- ldo9: LDO9 { /* SDCARD I/O */
- regulator-name = "VOUT9_1V8_2V95";
+ ldo9: LDO9 {
+ regulator-compatible = "hi6421v530_ldo9";
+ regulator-name = "LDO9";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <240>;
};
- ldo11: LDO11 { /* Low Speed Connector */
- regulator-name = "VOUT11_1V8_2V95";
+ ldo10: LDO10 {
+ regulator-compatible = "hi6421v530_ldo10";
+ regulator-name = "LDO10";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo13: LDO13 {
+ regulator-compatible = "hi6421v530_ldo13";
+ regulator-name = "LDO13";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3300000>;
- regulator-enable-ramp-delay = <240>;
+ regulator-enable-ramp-delay = <120>;
};
- ldo15: LDO15 { /* UFS VCC */
- regulator-name = "VOUT15_3V0";
+ ldo15: LDO15 {
+ regulator-compatible = "hi6421v530_ldo15";
+ regulator-name = "LDO15";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3000000>;
- regulator-boot-on;
regulator-always-on;
regulator-enable-ramp-delay = <120>;
};
- ldo16: LDO16 { /* SD VDD */
- regulator-name = "VOUT16_2V95";
+ ldo16: LDO16 {
+ regulator-compatible = "hi6421v530_ldo16";
+ regulator-name = "LDO16";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <360>;
};
- };
- };
- wlan_en: wlan-en-1-8v {
- compatible = "regulator-fixed";
- regulator-name = "wlan-en-regulator";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ ldo17: LDO17 {
+ regulator-compatible = "hi6421v530_ldo17";
+ regulator-name = "LDO17";
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <120>;
+ };
- /* GPIO_051_WIFI_EN */
- gpio = <&gpio6 3 0>;
+ ldo19: LDO19 {
+ regulator-compatible = "hi6421v530_ldo19";
+ regulator-name = "LDO19";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <120>;
+ };
- /* WLAN card specific delay */
- startup-delay-us = <70000>;
- enable-active-high;
- };
+ ldo20: LDO20 {
+ regulator-compatible = "hi6421v530_ldo20";
+ regulator-name = "LDO20";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-enable-ramp-delay = <120>;
+ };
- smmu {
- compatible = "hisi,hisi-smmu";
- phy_pgd_base = <0x0 0x34A78000>;
- };
+ ldo24: LDO24 {
+ regulator-compatible = "hi6421v530_ldo24";
+ regulator-name = "LDO24";
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <120>;
+ };
- smmu_lpae{
- compatible = "hisi,hisi-smmu-lpae";
- status = "ok";
+ ldo25: LDO25 {
+ regulator-compatible = "hi6421v530_ldo25";
+ regulator-name = "LDO25";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo31: LDO31 {
+ regulator-compatible = "hi6421v530_ldo31";
+ regulator-name = "LDO31";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo32: LDO32 {
+ regulator-compatible = "hi6421v530_ldo32";
+ regulator-name = "LDO32";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+ };
};
/* bluetooth - TI WL1837 */
kim {
compatible = "kim";
pinctrl-names = "default";
- pinctrl-0 = <&uart4_pmx_func &i2s0_pmx_func
- &uart4_cfg_func &i2s0_cfg_func>;
+ pinctrl-0 = <&uart4_pmx_func &i2s0_pmx_func &uart4_cfg_func &i2s0_cfg_func>;
/*
* FIXME: The following is complete CRAP since
* the vendor driver doesn't follow the gpio
@@ -247,74 +252,128 @@
btwilink {
compatible = "btwilink";
};
-};
-&i2c0 {
- /* On Low speed expansion */
- label = "LS-I2C0";
- status = "okay";
-};
+ /* power control mechanism for WLAN_EN */
+ wlan_en_reg: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "wlan-en-regulator";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
-&i2c1 {
- status = "okay";
+ /* WLAN_EN GPIO for this board - GPIO_051_WIFI_EN */
+ gpio = <&gpio6 3 0>;
- adv7533: adv7533@39 {
- status = "ok";
- compatible = "adi,adv7533";
- reg = <0x39>;
+ /* WLAN card specific delay */
+ startup-delay-us = <70000>;
+ enable-active-high;
};
-};
-&i2c7 {
- /* On Low speed expansion */
- label = "LS-I2C1";
- status = "okay";
-};
+ keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;
-&uart3 {
- /* On Low speed expansion */
- label = "LS-UART0";
- status = "okay";
-};
+ power {
+ wakeup-source;
+ gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+ };
+ };
-&uart4 {
- status = "okay";
+ leds_v1 {
+ compatible = "gpio-leds_v1";
+ status = "disabled";
+ user_led1 {
+ label = "user_led1";
+ gpios = <&gpio18 6 0>; /* <&gpio_150_user_led1>; */
+ linux,default-trigger = "heartbeat";
+ };
+
+ user_led2 {
+ label = "user_led2";
+ gpios = <&gpio18 7 0>; /* <&gpio_151_user_led2>; */
+ linux,default-trigger = "mmc0"; /* microSD card */
+ };
+
+ user_led3 {
+ label = "user_led3";
+ gpios = <&gpio23 5 0>; /* <&gpio_189_user_led3>; */
+ default-state = "off";
+ };
+
+ user_led4 {
+ label = "user_led4";
+ gpios = <&gpio23 6 0>; /* <&gpio_190_user_led4>; */
+ linux,default-trigger = "cpu0";
+ };
- bluetooth {
- compatible = "ti,wl1837-st";
- enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>;
- max-speed = <921600>;
+ wlan_active_led {
+ label = "wifi_active";
+ gpios = <&gpio25 5 0>; /* <&gpio_205_wifi_active>; */
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ bt_active_led {
+ label = "bt_active";
+ gpios = <&gpio25 7 0>; /* <&gpio_207_user_led1>; */
+ linux,default-trigger = "hci0rx";
+ default-state = "off";
+ };
};
-};
-&uart6 {
- /* On Low speed expansion */
- label = "LS-UART1";
- status = "okay";
-};
+ leds_v2 {
+ compatible = "gpio-leds_v2";
+ status = "disabled";
+ user_led1 {
+ label = "user_led1";
+ gpios = <&gpio18 6 0>; /* <&gpio_150_user_led1>; */
+ linux,default-trigger = "heartbeat";
+ };
-&spi2 {
- /* On Low speed expansion */
- label = "LS-SPI0";
- status = "disabled";
-};
+ user_led2 {
+ label = "user_led2";
+ gpios = <&gpio23 5 0>; /* <&gpio_189_user_led2>; */
+ linux,default-trigger = "mmc0"; /* microSD card */
+ };
-&spi3 {
- /* On High speed expansion */
- label = "HS-SPI1";
- status = "okay";
+ user_led3 {
+ label = "user_led3";
+ gpios = <&gpio23 6 0>; /* <&gpio_190_user_led3>; */
+ default-state = "off";
+ };
+
+ user_led4 {
+ label = "user_led4";
+ gpios = <&gpio26 3 0>; /* <&gpio_211_user_led4>; */
+ linux,default-trigger = "cpu0";
+ };
+
+ wlan_active_led {
+ label = "wifi_active";
+ gpios = <&gpio25 5 0>; /* <&gpio_205_wifi_active>; */
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ bt_active_led {
+ label = "bt_active";
+ gpios = <&gpio25 7 0>; /* <&gpio_207_user_led1>; */
+ linux,default-trigger = "hci0rx";
+ default-state = "off";
+ };
+ };
};
-&dwmmc1 {
- vmmc-supply = <&ldo16>;
- vqmmc-supply = <&ldo9>;
- status = "okay";
+&uart4 {
+ status = "ok";
};
&dwmmc2 { /* WIFI */
broken-cd;
/* WL_EN */
- vmmc-supply = <&wlan_en>;
+ vmmc-supply = <&wlan_en_reg>;
ti,non-removable;
non-removable;
#address-cells = <0x1>;
@@ -326,15 +385,6 @@
reg = <2>; /* sdio func num */
/* WL_IRQ, GPIO_179_WL_WAKEUP_AP */
interrupt-parent = <&gpio22>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <3 1>; /* IRQ_TYPE_EDGE_RISING */
};
};
-
-&ufs {
- ufs-hi3660-use-rate-B;
- ufs-hi3660-broken-fastauto;
- ufs-hi3660-use-HS-GEAR3;
- ufs-hi3660-broken-clk-gate-bypass;
- reset-gpio = <&gpio18 1 0>;
- status = "okay";
-};
old mode 100644
new mode 100755
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi3660-clock.h>
+#include <dt-bindings/reset/hisi,hi3660-resets.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -59,15 +60,15 @@
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
- next-level-cache = <&A53_L2>;
- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
+ clock-names = "cpu";
operating-points-v2 = <&cluster0_opp>;
+ sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
cooling-min-level = <4>;
cooling-max-level = <0>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <110>;
- sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
cpu1: cpu@1 {
@@ -75,9 +76,9 @@
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
- next-level-cache = <&A53_L2>;
- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
+ clock-names = "cpu";
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
@@ -87,9 +88,9 @@
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
- next-level-cache = <&A53_L2>;
- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
+ clock-names = "cpu";
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
@@ -99,9 +100,9 @@
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
- next-level-cache = <&A53_L2>;
- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
+ clock-names = "cpu";
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
@@ -111,19 +112,15 @@
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
- next-level-cache = <&A73_L2>;
- cpu-idle-states = <
- &CPU_NAP
- &CPU_SLEEP
- &CLUSTER_SLEEP_1
- >;
+ cpu-idle-states = <&CPU_NAP_0 &CPU_SLEEP_0 &CLUSTER_SLEEP_1>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
+ clock-names = "cpu";
operating-points-v2 = <&cluster1_opp>;
+ sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
cooling-min-level = <4>;
cooling-max-level = <0>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <550>;
- sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
};
cpu5: cpu@101 {
@@ -131,13 +128,9 @@
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
- next-level-cache = <&A73_L2>;
- cpu-idle-states = <
- &CPU_NAP
- &CPU_SLEEP
- &CLUSTER_SLEEP_1
- >;
+ cpu-idle-states = <&CPU_NAP_0 &CPU_SLEEP_0 &CLUSTER_SLEEP_1>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
+ clock-names = "cpu";
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
};
@@ -147,13 +140,9 @@
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
- next-level-cache = <&A73_L2>;
- cpu-idle-states = <
- &CPU_NAP
- &CPU_SLEEP
- &CLUSTER_SLEEP_1
- >;
+ cpu-idle-states = <&CPU_NAP_0 &CPU_SLEEP_0 &CLUSTER_SLEEP_1>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
+ clock-names = "cpu";
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
};
@@ -163,13 +152,9 @@
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
- next-level-cache = <&A73_L2>;
- cpu-idle-states = <
- &CPU_NAP
- &CPU_SLEEP
- &CLUSTER_SLEEP_1
- >;
+ cpu-idle-states = <&CPU_NAP_0 &CPU_SLEEP_0 &CLUSTER_SLEEP_1>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
+ clock-names = "cpu";
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
};
@@ -177,50 +162,43 @@
idle-states {
entry-method = "psci";
- CPU_NAP: cpu-nap {
+ CPU_NAP_0: cpu-nap-0 {
compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0000001>;
+ arm,psci-suspend-param = <0x0000000>;
entry-latency-us = <7>;
exit-latency-us = <2>;
min-residency-us = <15>;
+ local-timer-stop;
};
- CPU_SLEEP: cpu-sleep {
+ CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
- local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <40>;
exit-latency-us = <70>;
min-residency-us = <3000>;
+ local-timer-stop;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
- local-timer-stop;
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <500>;
exit-latency-us = <5000>;
min-residency-us = <20000>;
+ local-timer-stop;
};
CLUSTER_SLEEP_1: cluster-sleep-1 {
compatible = "arm,idle-state";
- local-timer-stop;
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <1000>;
exit-latency-us = <5000>;
min-residency-us = <20000>;
+ local-timer-stop;
};
};
- A53_L2: l2-cache0 {
- compatible = "cache";
- };
-
- A73_L2: l2-cache1 {
- compatible = "cache";
- };
-
/include/ "hi3660-sched-energy.dtsi"
};
@@ -306,26 +284,6 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
- pmu {
- compatible = "arm,armv8-pmuv3";
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>,
- <&cpu1>,
- <&cpu2>,
- <&cpu3>,
- <&cpu4>,
- <&cpu5>,
- <&cpu6>,
- <&cpu7>;
- };
-
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
@@ -336,6 +294,52 @@
clock-frequency = <1920000>;
};
+
+ /* display start */
+ framebuffer@E8600000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "hisilicon,hisifb";
+ fastboot_enable_flag = <0>;
+ fake_lcd_flag = <0>;
+ dss_base_phy = <0xE8600000>;
+ /*DSS, PERI_CRG, SCTRL, PCTRL, NOC_DSS_Service_Target, MMBUF_CFG*/
+ reg = <0 0xE8600000 0 0x80000>, <0 0xFFF35000 0 0x1000>, <0 0xFFF0A000 0 0x1000>, <0 0xE8A09000 0 0x1000>,
+ <0 0xE86C0000 0 0x10000>, <0 0xFFF02000 0 0x1000>, <0 0xFFF31000 0 0x1000>;
+ /*dss-pdp, dss-sdp, dss-adp, dss-dsi0, dss-dsi1 irq*/
+ interrupts = <0 245 4>, <0 246 4>, <0 247 4>, <0 251 4>, <0 252 4>;
+
+ clocks = <&crg_ctrl HI3660_ACLK_GATE_DSS>, <&crg_ctrl HI3660_PCLK_GATE_DSS>, <&crg_ctrl HI3660_CLK_GATE_EDC0>,
+ <&crg_ctrl HI3660_CLK_GATE_LDI0>, <&crg_ctrl HI3660_CLK_GATE_LDI1>, <&sctrl HI3660_CLK_GATE_DSS_AXI_MM>,
+ <&sctrl HI3660_PCLK_GATE_MMBUF>, <&crg_ctrl HI3660_CLK_GATE_TXDPHY0_REF>, <&crg_ctrl HI3660_CLK_GATE_TXDPHY1_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_TXDPHY0_CFG>, <&crg_ctrl HI3660_CLK_GATE_TXDPHY1_CFG>, <&crg_ctrl HI3660_PCLK_GATE_DSI0>,
+ <&crg_ctrl HI3660_PCLK_GATE_DSI1>;
+ clock-names = "aclk_dss", "pclk_dss", "clk_edc0", "clk_ldi0", "clk_ldi1",
+ "clk_dss_axi_mm", "pclk_mmbuf",
+ "clk_txdphy0_ref", "clk_txdphy1_ref", "clk_txdphy0_cfg", "clk_txdphy1_cfg",
+ "pclk_dsi0", "pclk_dsi1";
+ status = "disabled";
+
+ /*iommu_info {
+ start-addr = <0x8000>;
+ size = <0xbfff8000>;
+ };*/
+ };
+
+ panel_lcd_hikey {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "hisilicon,mipi_hikey";
+ lcd-bl-type = <0>;
+ lcd-display-type = <8>;
+ //vdd-supply = <&ldo3>;
+ lcd-ifbc-type = <0>;
+ gpios = <&gpio27 0 0>, <&gpio27 2 0>, <&gpio22 6 0>, <&gpio2 4 0>;
+ gpio_nums = <216 218 182 20>;
+ status = "disabled";
+ };
+ /* display start */
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -348,25 +352,12 @@
#clock-cells = <1>;
};
- crg_rst: crg_rst_controller {
- compatible = "hisilicon,hi3660-reset";
- #reset-cells = <2>;
- hisi,rst-syscon = <&crg_ctrl>;
- };
-
-
pctrl: pctrl@e8a09000 {
compatible = "hisilicon,hi3660-pctrl", "syscon";
reg = <0x0 0xe8a09000 0x0 0x2000>;
#clock-cells = <1>;
};
- pmctrl: pmctrl@fff31000 {
- compatible = "hisilicon,hi3660-pmctrl", "syscon";
- reg = <0x0 0xfff31000 0x0 0x1000>;
- #clock-cells = <1>;
- };
-
pmuctrl: crg_ctrl@fff34000 {
compatible = "hisilicon,hi3660-pmuctrl", "syscon";
reg = <0x0 0xfff34000 0x0 0x1000>;
@@ -379,6 +370,12 @@
#clock-cells = <1>;
};
+ pmctrl: pmctrl@fff31000 {
+ compatible = "hisilicon,hi3660-pmctrl", "syscon";
+ reg = <0x0 0xfff31000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
reboot {
compatible = "hisilicon,hi3660-reboot";
pmu-regmap = <&pmuctrl>;
@@ -386,19 +383,6 @@
reboot-offset = <0x4>;
};
- iomcu: iomcu@ffd7e000 {
- compatible = "hisilicon,hi3660-iomcu", "syscon";
- reg = <0x0 0xffd7e000 0x0 0x1000>;
- #clock-cells = <1>;
-
- };
-
- iomcu_rst: reset {
- compatible = "hisilicon,hi3660-reset";
- hisi,rst-syscon = <&iomcu>;
- #reset-cells = <2>;
- };
-
mailbox: mailbox@e896b000 {
compatible = "hisilicon,hi3660-mbox";
reg = <0x0 0xe896b000 0x0 0x1000>;
@@ -409,46 +393,109 @@
stub_clock: stub_clock {
compatible = "hisilicon,hi3660-stub-clk";
- reg = <0x0 0xe896b500 0x0 0x0100>;
+ reg = <0x0 0xe896b000 0x0 0x1000>;
#clock-cells = <1>;
mbox-names = "mbox-tx";
mboxes = <&mailbox 13 3 0>;
};
- dual_timer0: timer@fff14000 {
+ timer0: timer@fff14000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x0 0xfff14000 0x0 0x1000>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 48 4>, <0 49 4>;
clocks = <&crg_ctrl HI3660_OSC32K>,
<&crg_ctrl HI3660_OSC32K>,
<&crg_ctrl HI3660_OSC32K>;
clock-names = "timer1", "timer2", "apb_pclk";
};
- i2c0: i2c@ffd71000 {
+ ufs: ufs@ff3b0000 {
+ compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs";
+ reg = <0x0 0xff3b0000 0x0 0x1000>, /* 0: HCI standard */
+ <0x0 0xff3b1000 0x0 0x1000>; /* 1: UFS SYS CTRL */
+ interrupt-parent = <&gic>;
+ interrupts = <0 278 4>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
+ clock-names = "clk_ref", "clk_phy";
+ freq-table-hz = <0 0>, <0 0>;
+ resets = <&crg_rst HI3660_RST_UFS>,
+ <&crg_rst HI3660_RST_UFS_ASSERT>;
+ reset-names = "rst", "assert";
+ ufs-hi3660-use-rate-B;
+ ufs-hi3660-broken-fastauto;
+ ufs-hi3660-use-HS-GEAR3;
+ ufs-hi3660-unipro-termination;
+ ufs-hi3660-broken-clk-gate-bypass;
+ status = "ok";
+ };
+
+ iomcu: iomcu@ffd7e000 {
+ compatible = "hisilicon,hi3660-iomcu", "syscon";
+ reg = <0x0 0xffd7e000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ iomcu_rst: iomcu_rst_controller {
+ compatible = "hisilicon,hi3660-reset-iomcu";
+ #reset-cells = <1>;
+ hisi,rst-syscon = <&iomcu>;
+ };
+
+ crg_rst: crg_rst_controller {
+ compatible = "hisilicon,hi3660-reset-crgctrl";
+ #reset-cells = <1>;
+ hisi,rst-syscon = <&crg_ctrl>;
+ };
+
+ i2c0: i2c@FFD71000 {
compatible = "snps,designware-i2c";
- reg = <0x0 0xffd71000 0x0 0x1000>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
+ reg = <0x0 0xFFD71000 0x0 0x1000>;
+ interrupts = <0 118 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
- resets = <&iomcu_rst 0x20 3>;
+ resets = <&iomcu_rst HI3660_RST_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
- status = "disabled";
+ status = "ok";
};
- i2c1: i2c@ffd72000 {
+ i2c4: i2c@FDF0D000 {
compatible = "snps,designware-i2c";
- reg = <0x0 0xffd72000 0x0 0x1000>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
+ reg = <0x0 0xFDF0D000 0x0 0x1000>;
+ interrupts = <0 82 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C4>;
+ resets = <&crg_rst HI3660_RST_I2C4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pmx_func &i2c4_cfg_func>;
+ status = "ok";
+
+ fairchild_fsa9685: fsa9685@25 {
+ compatible = "hisilicon,fairchild_fsa9685";
+ reg = <0x25>;
+ fairchild_fsa9685,gpio-intb = <&gpio25 6 0>;
+ usbid-enable = <1>;
+ fcp_support = <1>;
+ scp_support = <0>;
+ mhl_detect_disable = <1>;
+ status = "ok";
+ };
+ };
+
+ i2c1: i2c@FFD72000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xFFD72000 0x0 0x1000>;
+ interrupts = <0 119 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
- resets = <&iomcu_rst 0x20 4>;
+ resets = <&iomcu_rst HI3660_RST_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
status = "ok";
@@ -470,6 +517,7 @@
rt-tcpc,rp_level = <0>;
/* the number of notifier supply */
rt-tcpc,notifier_supply_num = <0>;
+
pd-data {
pd,source-pdo-size = <1>;
/*<0x019014>;*/
@@ -477,11 +525,12 @@
pd,sink-pdo-size = <2>;
/* 0x0002d0c8 : 9V, 2A */
- pd,sink-pdo-data = <0x000190c8 0x0002d0c8> ;
+ pd,sink-pdo-data = <0x000190c8 0x0002d0c8>;
pd,id-vdo-size = <3>;
pd,id-vdo-data = <0xd00029cf 0x0 0x00010000>;
};
+
dpm_caps {
local_dr_power;
local_dr_data;
@@ -518,7 +567,7 @@
status = "ok";
compatible = "adi,adv7533";
reg = <0x39>;
- v1p2-supply = <&ldo3>;
+ v1p2-supply = <&ldo1>;
vdd-supply = <&ldo3>;
interrupt-parent = <&gpio1>;
interrupts = <1 2>;
@@ -564,35 +613,49 @@
status = "disabled";
};
- i2c3: i2c@fdf0c000 {
+ i2c2: i2c@FFD73000 {
compatible = "snps,designware-i2c";
- reg = <0x0 0xfdf0c000 0x0 0x1000>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
+ reg = <0x0 0xFFD73000 0x0 0x1000>;
+ interrupts = <0 120 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C2>;
+ resets = <&iomcu_rst HI3660_RST_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
+ status = "ok";
+ };
+
+ i2c3: i2c@FDF0C000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xFDF0C000 0x0 0x1000>;
+ interrupts = <0 81 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
- resets = <&crg_rst 0x78 7>;
+ resets = <&crg_rst HI3660_RST_I2C3>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
- status = "disabled";
+ status = "ok";
};
- i2c7: i2c@fdf0b000 {
+ i2c7: i2c@FDF0B000 {
compatible = "snps,designware-i2c";
- reg = <0x0 0xfdf0b000 0x0 0x1000>;
- interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
+ reg = <0x0 0xFDF0B000 0x0 0x1000>;
+ interrupts = <0 314 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
- resets = <&crg_rst 0x60 14>;
+ resets = <&crg_rst HI3660_RST_I2C7>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
- status = "disabled";
+ status = "ok";
};
- uart0: serial@fdf02000 {
+ uart0: uart@fdf02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf02000 0x0 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
@@ -604,7 +667,7 @@
status = "disabled";
};
- uart1: serial@fdf00000 {
+ uart1: uart@fdf00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf00000 0x0 0x1000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -616,7 +679,7 @@
status = "disabled";
};
- uart2: serial@fdf03000 {
+ uart2: uart@fdf03000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf03000 0x0 0x1000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -628,7 +691,7 @@
status = "disabled";
};
- uart3: serial@ffd74000 {
+ uart3: uart@ffd74000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xffd74000 0x0 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -638,9 +701,9 @@
pinctrl-names = "default";
pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
status = "disabled";
- };
+ };
- uart4: serial@fdf01000 {
+ uart4: uart@fdf01000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf01000 0x0 0x1000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
@@ -652,7 +715,7 @@
status = "disabled";
};
- uart5: serial@fdf05000 {
+ uart5: uart@fdf05000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf05000 0x0 0x1000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
@@ -664,7 +727,7 @@
status = "disabled";
};
- uart6: serial@fff32000 {
+ uart6: uart@fff32000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfff32000 0x0 0x1000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
@@ -684,10 +747,55 @@
clock-names = "apb_pclk";
};
+ spi1: spi@fdf08000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xfdf08000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 80 4>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SPI1>;
+ clock-names = "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pmx_func &spi1_cfg_func>;
+ num-cs = <1>;
+ cs-gpios = <&gpio2 2 0>;
+ status = "disabled";
+ };
+
+ spi3: spi@ff3b3000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xff3b3000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 312 4>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
+ clock-names = "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;
+ num-cs = <1>;
+ cs-gpios = <&gpio18 5 0>;
+ status = "disabled";
+ };
+
+ spi4: spi@fdf06000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xfdf06000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 313 4>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SPI4>;
+ clock-names = "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi4_pmx_func &spi4_cfg_func>;
+ num-cs = <1>;
+ cs-gpios = <&gpio27 2 0>;
+ status = "disabled";
+ };
+
gpio0: gpio@e8a0b000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell0";
reg = <0 0xe8a0b000 0 0x1000>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 84 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 1 0 7>;
@@ -695,12 +803,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio1: gpio@e8a0c000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell1";
reg = <0 0xe8a0c000 0 0x1000>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 85 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 1 7 7>;
@@ -708,12 +817,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio2: gpio@e8a0d000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell2";
reg = <0 0xe8a0d000 0 0x1000>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 86 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 14 8>;
@@ -721,12 +831,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio3: gpio@e8a0e000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell3";
reg = <0 0xe8a0e000 0 0x1000>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 87 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 22 8>;
@@ -734,12 +845,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio4: gpio@e8a0f000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell4";
reg = <0 0xe8a0f000 0 0x1000>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 88 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 30 8>;
@@ -747,12 +859,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio5: gpio@e8a10000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell5";
reg = <0 0xe8a10000 0 0x1000>;
- interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 89 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 38 8>;
@@ -760,12 +873,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio6: gpio@e8a11000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell6";
reg = <0 0xe8a11000 0 0x1000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 90 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 46 8>;
@@ -773,12 +887,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio7: gpio@e8a12000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell7";
reg = <0 0xe8a12000 0 0x1000>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 91 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 54 8>;
@@ -786,12 +901,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio8: gpio@e8a13000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell8";
reg = <0 0xe8a13000 0 0x1000>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 92 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 62 8>;
@@ -799,12 +915,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio9: gpio@e8a14000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell9";
reg = <0 0xe8a14000 0 0x1000>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 93 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 70 8>;
@@ -812,12 +929,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio10: gpio@e8a15000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell10";
reg = <0 0xe8a15000 0 0x1000>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 94 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 78 8>;
@@ -825,12 +943,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio11: gpio@e8a16000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell11";
reg = <0 0xe8a16000 0 0x1000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 95 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 86 8>;
@@ -838,12 +957,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio12: gpio@e8a17000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell12";
reg = <0 0xe8a17000 0 0x1000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 96 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
@@ -851,12 +971,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio13: gpio@e8a18000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell13";
reg = <0 0xe8a18000 0 0x1000>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 97 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 102 8>;
@@ -864,12 +985,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio14: gpio@e8a19000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell14";
reg = <0 0xe8a19000 0 0x1000>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 98 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 110 8>;
@@ -877,12 +999,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio15: gpio@e8a1a000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell15";
reg = <0 0xe8a1a000 0 0x1000>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 99 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 118 6>;
@@ -890,36 +1013,39 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio16: gpio@e8a1b000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell16";
reg = <0 0xe8a1b000 0 0x1000>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 100 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio17: gpio@e8a1c000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell17";
reg = <0 0xe8a1c000 0 0x1000>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 101 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio18: gpio@ff3b4000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell18";
reg = <0 0xff3b4000 0 0x1000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 102 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx2 0 0 8>;
@@ -927,12 +1053,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio19: gpio@ff3b5000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell19";
reg = <0 0xff3b5000 0 0x1000>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 103 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx2 0 8 4>;
@@ -940,12 +1067,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio20: gpio@e8a1f000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell20";
reg = <0 0xe8a1f000 0 0x1000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 104 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx1 0 0 6>;
@@ -953,12 +1081,13 @@
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio21: gpio@e8a20000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell21";
reg = <0 0xe8a20000 0 0x1000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 105 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -966,12 +1095,13 @@
gpio-ranges = <&pmx3 0 0 6>;
clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio22: gpio@fff0b000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell22";
reg = <0 0xfff0b000 0 0x1000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 106 0x4>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO176 */
@@ -980,12 +1110,13 @@
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio23: gpio@fff0c000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell23";
reg = <0 0xfff0c000 0 0x1000>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 107 0x4>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO184 */
@@ -994,12 +1125,13 @@
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
clock-names = "apb_pclk";
+ status = "ok";
};
- gpio24: gpio@fff0d000 {
- compatible = "arm,pl061", "arm,primecell";
+ gpio24: gpio@fff0d000 {
+ compatible = "arm,pl061", "arm,primecell", "hisi,poweroff", "arm,primecell24";
reg = <0 0xfff0d000 0 0x1000>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 108 0x4>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO192 */
@@ -1008,12 +1140,13 @@
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio25: gpio@fff0e000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell25";
reg = <0 0xfff0e000 0 0x1000>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 109 0x4>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO200 */
@@ -1022,12 +1155,13 @@
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio26: gpio@fff0f000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell26";
reg = <0 0xfff0f000 0 0x1000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 110 0x4>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO208 */
@@ -1036,12 +1170,13 @@
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio27: gpio@fff10000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell27";
reg = <0 0xfff10000 0 0x1000>;
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 111 0x4>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO216 */
@@ -1050,88 +1185,24 @@
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
clock-names = "apb_pclk";
+ status = "ok";
};
gpio28: gpio@fff1d000 {
- compatible = "arm,pl061", "arm,primecell";
+ compatible = "arm,pl061", "arm,primecell", "arm,primecell28";
reg = <0 0xfff1d000 0 0x1000>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 141 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
clock-names = "apb_pclk";
- };
-
- spi2: spi@ffd68000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x0 0xffd68000 0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
- clock-names = "apb_pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pmx_func>;
- num-cs = <1>;
- cs-gpios = <&gpio27 2 0>;
- status = "disabled";
- };
-
- spi3: spi@ff3b3000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x0 0xff3b3000 0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
- clock-names = "apb_pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&spi3_pmx_func>;
- num-cs = <1>;
- cs-gpios = <&gpio18 5 0>;
- status = "disabled";
- };
-
- pcie@f4000000 {
- compatible = "hisilicon,kirin960-pcie";
- reg = <0x0 0xf4000000 0x0 0x1000>,
- <0x0 0xff3fe000 0x0 0x1000>,
- <0x0 0xf3f20000 0x0 0x40000>,
- <0x0 0xf5000000 0x0 0x2000>;
- reg-names = "dbi", "apb", "phy", "config";
- bus-range = <0x0 0x1>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x02000000 0x0 0x00000000
- 0x0 0xf6000000
- 0x0 0x02000000>;
- num-lanes = <1>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map = <0x0 0 0 1
- &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
- <0x0 0 0 2
- &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
- <0x0 0 0 3
- &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
- <0x0 0 0 4
- &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
- <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
- <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
- <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
- <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
- clock-names = "pcie_phy_ref", "pcie_aux",
- "pcie_apb_phy", "pcie_apb_sys",
- "pcie_aclk";
- reset-gpios = <&gpio11 1 0 >;
+ status = "ok";
};
/* SD */
- dwmmc1: dwmmc1@ff37f000 {
+ dwmmc1: dwmmc1@FF37F000 {
#address-cells = <1>;
#size-cells = <0>;
cd-inverted;
@@ -1143,24 +1214,22 @@
supports-highspeed;
card-detect-delay = <200>;
reg = <0x0 0xff37f000 0x0 0x1000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 139 4>;
clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
<&crg_ctrl HI3660_HCLK_GATE_SD>;
clock-names = "ciu", "biu";
clock-frequency = <3200000>;
- resets = <&crg_rst 0x94 18>;
+ resets = <&crg_rst HI3660_RST_SD>;
cd-gpios = <&gpio25 3 0>;
hisilicon,peripheral-syscon = <&sctrl>;
pinctrl-names = "default";
- pinctrl-0 = <&sd_pmx_func
- &sd_clk_cfg_func
- &sd_cfg_func>;
+ pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
+ vmmc-supply = <&ldo16>;
+ vqmmc-supply = <&ldo9>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
- status = "disabled";
-
slot@0 {
reg = <0x0>;
bus-width = <4>;
@@ -1169,51 +1238,23 @@
};
/* SDIO */
- dwmmc2: dwmmc2@ff3ff000 {
+ dwmmc2: dwmmc2@FF3FF000 {
compatible = "hisilicon,hi3660-dw-mshc";
reg = <0x0 0xff3ff000 0x0 0x1000>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 140 4>;
num-slots = <1>;
clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
<&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
clock-names = "ciu", "biu";
- resets = <&crg_rst 0x94 20>;
+ resets = <&crg_rst HI3660_RST_SDIO>;
card-detect-delay = <200>;
supports-highspeed;
keep-power-in-suspend;
pinctrl-names = "default";
- pinctrl-0 = <&sdio_pmx_func
- &sdio_clk_cfg_func
- &sdio_cfg_func>;
+ pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
status = "disabled";
};
- tsensor: tsensor {
- compatible = "hisilicon,hi3660-thermal";
- reg = <0x0 0xfff30000 0x0 0x1000>;
- #thermal-sensor-cells = <1>;
- };
-
- ufs: ufs@ff3b0000 {
- compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs";
- /* 0: HCI standard */
- /* 1: UFS SYS CTRL */
- reg = <0x0 0xff3b0000 0x0 0x1000>,
- <0x0 0xff3b1000 0x0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
- <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
- clock-names = "clk_ref", "clk_phy";
- freq-table-hz = <0 0>, <0 0>;
- /* offset: 0x84; bit: 12 */
- /* offset: 0x84; bit: 7 */
- resets = <&crg_rst 0x84 12>,
- <&crg_rst 0x84 7>;
- reset-names = "rst", "assert";
- };
-
-
hub5734_gpio:hub5734_gpio {
compatible = "hub5734_gpio";
pinctrl-names = "default";
@@ -1229,7 +1270,7 @@
bc_again_flag = <1>;
clocks = <&crg_ctrl HI3660_CLK_ABB_USB>,
- <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
+ <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
clock-names = "clk_usb3phy_ref", "aclk_usb3otg";
eye_diagram_param = <0x1c466e3>;
eye_diagram_host_param = <0x1c466e3>;
@@ -1246,6 +1287,57 @@
};
};
+ i2s0: hisi_i2s {
+ compatible = "hisilicon,hisi-i2s";
+ reg = <0x0 0xe804f800 0x0 0x400>,
+ <0x0 0xe804e000 0x0 0x400>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s2_pmx_func &i2s2_cfg_func>;
+ dmas = <&asp_dmac 18 &asp_dmac 19>;
+ dma-names = "rx", "tx";
+ status = "ok";
+ #sound-dai-cells = <0>;
+ };
+
+ asp_dmac: asp_dmac@E804B000 {
+ compatible = "hisilicon,hisi-pcm-asp-dma";
+ reg = <0x0 0xe804b000 0x0 0x1000>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ dma-requests = <32>;
+ dma-min-chan = <0>;
+ dma-used-chans = <0xFFFE>;
+ dma-share;
+ interrupts = <0 216 4>;
+ interrupt-names = "asp_dma_irq";
+ status = "ok";
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "hikey-hdmi";
+ simple-audio-card,format = "i2s";
+
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+
+ sound_master: simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&adv7533>;
+ };
+ };
+
+ tsensor: tsensor {
+ compatible = "hisilicon,thermal-hi3660";
+ mbox-names = "mbox-tx";
+ mboxes = <&mailbox 28 3 0>;
+ #thermal-sensor-cells = <1>;
+ status = "ok";
+ };
+
thermal-zones {
cls0: cls0 {
@@ -1254,7 +1346,7 @@
sustainable-power = <4500>;
/* sensor ID */
- thermal-sensors = <&tsensor 4>;
+ thermal-sensors = <&tsensor 0>;
trips {
threshold: trip-point@0 {
@@ -1281,55 +1373,42 @@
contribution = <512>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
- map2 {
- trip = <&target>;
- contribution = <1024>;
- cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
};
};
};
+ };
- i2s0: hisi_i2s {
- compatible = "hisilicon,hisi-i2s";
- reg = <0x0 0xe804f800 0x0 0x400>,
- <0x0 0xe804e000 0x0 0x400>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s2_pmx_func>;
- dmas = <&asp_dmac 18 &asp_dmac 19>;
- dma-names = "rx", "tx";
- #sound-dai-cells = <0>;
- };
-
- asp_dmac: asp_dmac@E804B000 {
- compatible = "hisilicon,hisi-pcm-asp-dma";
- reg = <0x0 0xe804b000 0x0 0x1000>;
- #dma-cells = <1>;
- dma-channels = <16>;
- dma-requests = <32>;
- dma-min-chan = <0>;
- dma-used-chans = <0xFFFE>;
- dma-share;
- interrupts = <0 216 4>;
- interrupt-names = "asp_dma_irq";
- status = "ok";
- };
-
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "hikey-hdmi";
- simple-audio-card,format = "i2s";
-
- simple-audio-card,bitclock-master = <&sound_master>;
- simple-audio-card,frame-master = <&sound_master>;
-
- sound_master: simple-audio-card,cpu {
- sound-dai = <&i2s0>;
- };
+ its_pcie: interrupt-controller@f4000000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x0 0xf7000000 0x0 0x100000>;
+ };
- simple-audio-card,codec {
- sound-dai = <&adv7533>;
- };
- };
+ kirin_pcie_rc@0xf4000000 {
+ compatible = "hisilicon,kirin-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF5000000 0 0x2000>;
+ reg-names = "dbi","apb","phy", "config";
+ bus-range = <0x0 0x1>;
+ msi-parent = <&its_pcie>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0 0xf4000000 0x0 0x4000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic 0 0 0 282 4>,
+ <0 0 0 2 &gic 0 0 0 283 4>,
+ <0 0 0 3 &gic 0 0 0 284 4>,
+ <0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+ interrupts = <0 283 4>;
+ interrupt-names = "INTb";
+ reset-gpio = <&gpio11 1 0 >;
+ eye_param_ctrl2 = <0x1540AA4B>;
+ eye_param_ctrl3 = <0x14003FFF>;
};
};
@@ -11,11 +11,9 @@
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
-
pmx0: pinmux@e896c000 {
compatible = "pinctrl-single";
reg = <0x0 0xe896c000 0x0 0x1f0>;
- #pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
@@ -33,18 +31,6 @@
>;
};
- csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func {
- pinctrl-single,pins = <
- 0x044 MUX_M0 /* CSI0_PWD_N */
- >;
- };
-
- csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func {
- pinctrl-single,pins = <
- 0x04c MUX_M0 /* CSI1_PWD_N */
- >;
- };
-
isp0_pmx_func: isp0_pmx_func {
pinctrl-single,pins = <
0x058 MUX_M1 /* ISP_CLK0 */
@@ -81,16 +67,19 @@
>;
};
- pcie_perstn_pmx_func: pcie_perstn_pmx_func {
+ usbhub5734_pmx_func: usbhub5734_pmx_func {
pinctrl-single,pins = <
- 0x15c MUX_M1 /* PCIE_PERST_N */
+ 0x11c MUX_M0 /* GPIO_073 */
+ 0x120 MUX_M0 /* GPIO_074 */
>;
};
- usbhub5734_pmx_func: usbhub5734_pmx_func {
+ spi1_pmx_func: spi1_pmx_func {
pinctrl-single,pins = <
- 0x11c MUX_M0 /* GPIO_073 */
- 0x120 MUX_M0 /* GPIO_074 */
+ 0x034 MUX_M1 /* SPI1_CLK */
+ 0x038 MUX_M1 /* SPI1_DI */
+ 0x03c MUX_M1 /* SPI1_DO */
+ 0x040 MUX_M1 /* SPI1_CS_N */
>;
};
@@ -154,18 +143,6 @@
0x0d8 MUX_M1 /* UART6_TXD */
>;
};
-
- cam0_rst_pmx_func: cam0_rst_pmx_func {
- pinctrl-single,pins = <
- 0x0c8 MUX_M0 /* CAM0_RST */
- >;
- };
-
- cam1_rst_pmx_func: cam1_rst_pmx_func {
- pinctrl-single,pins = <
- 0x124 MUX_M0 /* CAM1_RST */
- >;
- };
};
/* [IOMG_MMC0_000, IOMG_MMC0_005] */
@@ -173,7 +150,6 @@
compatible = "pinctrl-single";
reg = <0x0 0xff37e000 0x0 0x18>;
#gpio-range-cells = <0x3>;
- #pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
@@ -195,7 +171,6 @@
pmx2: pinmux@ff3b6000 {
compatible = "pinctrl-single";
reg = <0x0 0xff3b6000 0x0 0x30>;
- #pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
@@ -223,7 +198,6 @@
pmx3: pinmux@ff3fd000 {
compatible = "pinctrl-single";
reg = <0x0 0xff3fd000 0x0 0x18>;
- #pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
@@ -246,7 +220,6 @@
pmx4: pinmux@fff11000 {
compatible = "pinctrl-single";
reg = <0x0 0xfff11000 0x0 0xa8>;
- #pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
@@ -283,6 +256,13 @@
>;
};
+ i2c2_pmx_func: i2c2_pmx_func {
+ pinctrl-single,pins = <
+ 0x024 MUX_M1 /* I2C2_SCL */
+ 0x028 MUX_M1 /* I2C2_SDA */
+ >;
+ };
+
i2c7_pmx_func: i2c7_pmx_func {
pinctrl-single,pins = <
0x024 MUX_M3 /* I2C7_SCL */
@@ -306,6 +286,15 @@
>;
};
+ spi4_pmx_func: spi4_pmx_func {
+ pinctrl-single,pins = <
+ 0x08c MUX_M4 /* SPI4_CLK */
+ 0x090 MUX_M4 /* SPI4_DI */
+ 0x094 MUX_M4 /* SPI4_DO */
+ 0x098 MUX_M4 /* SPI4_CS0_N */
+ >;
+ };
+
i2s0_pmx_func: i2s0_pmx_func {
pinctrl-single,pins = <
0x034 MUX_M1 /* I2S0_DI */
@@ -319,8 +308,9 @@
pmx5: pinmux@e896c800 {
compatible = "pinconf-single";
reg = <0x0 0xe896c800 0x0 0x200>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-single,register-width = <32>;
pmu_cfg_func: pmu_cfg_func {
pinctrl-single,pins = <
@@ -329,21 +319,9 @@
0x018 0x0 /* PMU_CLKOUT */
0x10c 0x0 /* PMU_HKADC_SSI */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_06MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
i2c3_cfg_func: i2c3_cfg_func {
@@ -351,63 +329,21 @@
0x038 0x0 /* I2C3_SCL */
0x03c 0x0 /* I2C3_SDA */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
- csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func {
+ spi1_cfg_func: spi1_cfg_func {
pinctrl-single,pins = <
- 0x050 0x0 /* CSI0_PWD_N */
- >;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_04MA DRIVE6_MASK
- >;
- };
-
- csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func {
- pinctrl-single,pins = <
- 0x058 0x0 /* CSI1_PWD_N */
- >;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_04MA DRIVE6_MASK
+ 0x040 0x0 /* SPI1_CLK */
+ 0x044 0x0 /* SPI1_DI */
+ 0x048 0x0 /* SPI1_DO */
+ 0x04c 0x0 /* SPI1_CS_N */
>;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
isp0_cfg_func: isp0_cfg_func {
@@ -416,20 +352,9 @@
0x070 0x0 /* ISP_SCL0 */
0x074 0x0 /* ISP_SDA0 */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_04MA DRIVE6_MASK>;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
isp1_cfg_func: isp1_cfg_func {
@@ -438,42 +363,28 @@
0x078 0x0 /* ISP_SCL1 */
0x07c 0x0 /* ISP_SDA1 */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_04MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
pwr_key_cfg_func: pwr_key_cfg_func {
pinctrl-single,pins = <
0x08c 0x0 /* GPIO_034 */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
+ };
+
+ i2c4_cfg_func: i2c4_cfg_func {
+ pinctrl-single,pins = <
+ 0x09c 0x0 /* I2C4_SCL */
+ 0x0a0 0x0 /* I2C4_SDA */
>;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
uart1_cfg_func: uart1_cfg_func {
@@ -483,21 +394,9 @@
0x0bc 0x0 /* UART1_CTS_N */
0x0c0 0x0 /* UART1_RTS_N */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
uart2_cfg_func: uart2_cfg_func {
@@ -507,21 +406,9 @@
0x0d0 0x0 /* UART2_TXD */
0x0d4 0x0 /* UART2_RXD */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
uart5_cfg_func: uart5_cfg_func {
@@ -531,42 +418,9 @@
0x0d0 0x0 /* UART5_CTS_N */
0x0d4 0x0 /* UART5_RTS_N */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
- };
-
- cam0_rst_cfg_func: cam0_rst_cfg_func {
- pinctrl-single,pins = <
- 0x0d4 0x0 /* CAM0_RST */
- >;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_04MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
uart0_cfg_func: uart0_cfg_func {
@@ -574,21 +428,9 @@
0x0d8 0x0 /* UART0_RXD */
0x0dc 0x0 /* UART0_TXD */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
uart6_cfg_func: uart6_cfg_func {
@@ -598,21 +440,9 @@
0x0e0 0x0 /* UART6_RXD */
0x0e4 0x0 /* UART6_TXD */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
uart3_cfg_func: uart3_cfg_func {
@@ -622,21 +452,9 @@
0x0f0 0x0 /* UART3_RXD */
0x0f4 0x0 /* UART3_TXD */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
uart4_cfg_func: uart4_cfg_func {
@@ -646,123 +464,56 @@
0x100 0x0 /* UART4_RXD */
0x104 0x0 /* UART4_TXD */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
- };
-
- cam1_rst_cfg_func: cam1_rst_cfg_func {
- pinctrl-single,pins = <
- 0x130 0x0 /* CAM1_RST */
- >;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_04MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
};
pmx6: pinmux@ff3b6800 {
compatible = "pinconf-single";
reg = <0x0 0xff3b6800 0x0 0x18>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-single,register-width = <32>;
ufs_cfg_func: ufs_cfg_func {
pinctrl-single,pins = <
0x000 0x0 /* UFS_REF_CLK */
0x004 0x0 /* UFS_RST_N */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_08MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_08MA DRIVE6_MASK>;
};
spi3_cfg_func: spi3_cfg_func {
pinctrl-single,pins = <
0x008 0x0 /* SPI3_CLK */
- 0x0 /* SPI3_DI */
+ 0x00c 0x0 /* SPI3_DI */
0x010 0x0 /* SPI3_DO */
0x014 0x0 /* SPI3_CS0_N */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
};
pmx7: pinmux@ff3fd800 {
compatible = "pinconf-single";
reg = <0x0 0xff3fd800 0x0 0x18>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-single,register-width = <32>;
sdio_clk_cfg_func: sdio_clk_cfg_func {
pinctrl-single,pins = <
0x000 0x0 /* SDIO_CLK */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE6_32MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE6_32MA DRIVE6_MASK>;
};
sdio_cfg_func: sdio_cfg_func {
@@ -773,50 +524,26 @@
0x010 0x0 /* SDIO_DATA2 */
0x014 0x0 /* SDIO_DATA3 */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_UP
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE6_19MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE6_19MA DRIVE6_MASK>;
};
};
pmx8: pinmux@ff37e800 {
compatible = "pinconf-single";
reg = <0x0 0xff37e800 0x0 0x18>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-single,register-width = <32>;
sd_clk_cfg_func: sd_clk_cfg_func {
pinctrl-single,pins = <
0x000 0x0 /* SD_CLK */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_DIS
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE6_32MA
- DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE6_32MA DRIVE6_MASK>;
};
sd_cfg_func: sd_cfg_func {
@@ -827,51 +554,27 @@
0x010 0x0 /* SD_DATA2 */
0x014 0x0 /* SD_DATA3 */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_UP
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE6_19MA
- DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE6_19MA DRIVE6_MASK>;
};
};
pmx9: pinmux@fff11800 {
compatible = "pinconf-single";
reg = <0x0 0xfff11800 0x0 0xbc>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-single,register-width = <32>;
i2c0_cfg_func: i2c0_cfg_func {
pinctrl-single,pins = <
0x01c 0x0 /* I2C0_SCL */
0x020 0x0 /* I2C0_SDA */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_UP
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
i2c1_cfg_func: i2c1_cfg_func {
@@ -879,21 +582,19 @@
0x024 0x0 /* I2C1_SCL */
0x028 0x0 /* I2C1_SDA */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_UP
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
+ };
+
+ i2c2_cfg_func: i2c2_cfg_func {
+ pinctrl-single,pins = <
+ 0x02c 0x0 /* I2C2_SCL */
+ 0x030 0x0 /* I2C2_SDA */
>;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
i2c7_cfg_func: i2c7_cfg_func {
@@ -901,21 +602,9 @@
0x02c 0x0 /* I2C7_SCL */
0x030 0x0 /* I2C7_SDA */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_UP
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
slimbus_cfg_func: slimbus_cfg_func {
@@ -923,21 +612,9 @@
0x034 0x0 /* SLIMBUS_CLK */
0x038 0x0 /* SLIMBUS_DATA */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_UP
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
i2s0_cfg_func: i2s0_cfg_func {
@@ -947,21 +624,9 @@
0x048 0x0 /* I2S0_XCLK */
0x04c 0x0 /* I2S0_XFS */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_UP
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
i2s2_cfg_func: i2s2_cfg_func {
@@ -971,21 +636,9 @@
0x058 0x0 /* I2S2_XCLK */
0x05c 0x0 /* I2S2_XFS */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_UP
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
pcie_cfg_func: pcie_cfg_func {
@@ -993,21 +646,9 @@
0x094 0x0 /* PCIE_CLKREQ_N */
0x098 0x0 /* PCIE_WAKE_N */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_UP
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
spi2_cfg_func: spi2_cfg_func {
@@ -1017,42 +658,30 @@
0x0a4 0x0 /* SPI2_DO */
0x0a8 0x0 /* SPI2_CS0_N */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_UP
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
+ };
+
+ spi4_cfg_func: spi4_cfg_func {
+ pinctrl-single,pins = <
+ 0x09c 0x0 /* SPI4_CLK */
+ 0x0a0 0x0 /* SPI4_DI */
+ 0x0a4 0x0 /* SPI4_DO */
+ 0x0a8 0x0 /* SPI4_CS0_N */
>;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
usb_cfg_func: usb_cfg_func {
pinctrl-single,pins = <
0x0ac 0x0 /* GPIO_219 */
>;
- pinctrl-single,bias-pulldown = <
- PULL_DIS
- PULL_DOWN
- PULL_DIS
- PULL_DOWN
- >;
- pinctrl-single,bias-pullup = <
- PULL_UP
- PULL_UP
- PULL_DIS
- PULL_UP
- >;
- pinctrl-single,drive-strength = <
- DRIVE7_02MA DRIVE6_MASK
- >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE7_02MA DRIVE6_MASK>;
};
};
};
@@ -280,8 +280,6 @@ CONFIG_THERMAL=y
CONFIG_THERMAL_EMULATION=y
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
-CONFIG_DEVFREQ_THERMAL=y
-CONFIG_HI3660_THERMAL=y
CONFIG_EXYNOS_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_RENESAS_WDT=y
@@ -325,7 +323,6 @@ CONFIG_SND_SOC=y
CONFIG_SND_SOC_RCAR=y
CONFIG_SND_SOC_SAMSUNG=y
CONFIG_SND_SOC_AK4613=y
-CONFIG_HUB_USB5734=y
CONFIG_USB=y
CONFIG_USB_OTG=y
CONFIG_USB_XHCI_HCD=y
@@ -341,20 +338,12 @@ CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_RENESAS_USBHS=m
CONFIG_USB_STORAGE=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_HISI=y
-CONFIG_USB_DWC3_OTG=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_ISP1760=y
-CONFIG_TCPC_CLASS=y
-CONFIG_USB_POWER_DELIVERY=y
-CONFIG_TCPC_RT1711H=y
-CONFIG_USB_PD_VBUS_STABLE_TOUT=125
-CONFIG_USB_PD_VBUS_PRESENT_TOUT=20
CONFIG_USB_HSIC_USB3503=y
CONFIG_USB_MSM_OTG=y
CONFIG_USB_ULPI=y
@@ -432,16 +421,13 @@ CONFIG_COMMON_RESET_HI6220=y
#
# ARM GPU Configuration
#
-CONFIG_PM_DEVFREQ=y
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_MALI_MIDGARD=y
# CONFIG_MALI_GATOR_SUPPORT is not set
-# CONFIG_MALI_MIDGARD_DVFS is not set
-CONFIG_MALI_DEVFREQ=y
+CONFIG_MALI_MIDGARD_DVFS=y
# CONFIG_MALI_MIDGARD_RT_PM is not set
# CONFIG_MALI_MIDGARD_ENABLE_TRACE is not set
# CONFIG_MALI_MIDGARD_DEBUG_SYS is not set
+# CONFIG_MALI_DEVFREQ is not set
CONFIG_MALI_EXPERT=y
# CONFIG_MALI_DEBUG_SHADER_SPLIT_FS is not set
CONFIG_MALI_PLATFORM_FAKE=y
@@ -60,15 +60,12 @@ CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_HISI_CPUIDLE=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPUFREQ_DT=y
CONFIG_NET=y
CONFIG_PACKET=y
@@ -282,8 +279,6 @@ CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_CPU_THERMAL=y
-CONFIG_DEVFREQ_THERMAL=y
-CONFIG_HI3660_THERMAL=y
CONFIG_HISI_THERMAL=y
CONFIG_MFD_HI6421_PMIC=y
CONFIG_MFD_HI655X_PMIC=y
@@ -362,7 +357,6 @@ CONFIG_HID_WACOM=y
CONFIG_HID_WIIMOTE=y
CONFIG_HID_ZEROPLUS=y
CONFIG_HID_ZYDACRON=y
-CONFIG_HUB_USB5734=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_XHCI_HCD=y
@@ -373,15 +367,11 @@ CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_ACM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_HISI=y
-CONFIG_USB_DWC3_OTG=y
CONFIG_USB_DWC2=y
CONFIG_USB_ISP1760=y
CONFIG_TCPC_CLASS=y
CONFIG_USB_POWER_DELIVERY=y
CONFIG_TCPC_RT1711H=y
-CONFIG_USB_PD_VBUS_STABLE_TOUT=125
-CONFIG_USB_PD_VBUS_PRESENT_TOUT=20
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=y
@@ -433,33 +423,7 @@ CONFIG_MAILBOX=y
CONFIG_HI6220_MBOX=y
CONFIG_HI3660_MBOX=y
CONFIG_HISI_IOMMU_LPAE=y
-#
-# ARM GPU Configuration
-#
-CONFIG_PM_DEVFREQ=y
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_MALI_MIDGARD=y
-# CONFIG_MALI_GATOR_SUPPORT is not set
-# CONFIG_MALI_MIDGARD_DVFS is not set
-CONFIG_MALI_DEVFREQ=y
-# CONFIG_MALI_MIDGARD_RT_PM is not set
-# CONFIG_MALI_MIDGARD_ENABLE_TRACE is not set
-# CONFIG_MALI_MIDGARD_DEBUG_SYS is not set
-CONFIG_MALI_EXPERT=y
-# CONFIG_MALI_DEBUG_SHADER_SPLIT_FS is not set
-CONFIG_MALI_PLATFORM_FAKE=y
-CONFIG_MALI_PLATFORM_HISILICON=y
-# CONFIG_MALI_DEBUG is not set
-# CONFIG_MALI_NO_MALI is not set
-# CONFIG_MALI_TRACE_TIMELINE is not set
-# CONFIG_MALI_SYSTEM_TRACE is not set
-# CONFIG_MALI_PM_DEMAND is not set
-CONFIG_REPORT_VSYNC=y
-CONFIG_MALI_IDLE_AUTO_CLK_DIV=y
-# CONFIG_MALI_DMA_FENCE is not set
-# CONFIG_MALI_PRFCNT_SET_SECONDARY is not set
-# CONFIG_FMC is not set
CONFIG_PHY_HI6220_USB=y
CONFIG_PHY_XGENE=y
CONFIG_ANDROID=y
@@ -468,7 +432,6 @@ CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder"
CONFIG_EFI_VARS=y
CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
CONFIG_ACPI=y
-CONFIG_F2FS_FS=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_ENCRYPTION=y
@@ -487,13 +450,10 @@ CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_HUGETLBFS=y
CONFIG_SQUASHFS=y
-CONFIG_SQUASHFS_FILE_DIRECT=y
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_LZ4=y
-CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
-CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
CONFIG_PSTORE=y
CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_PMSG=y
@@ -47,7 +47,7 @@ static int
kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags)
{
struct kbase_device *kbdev = dev_get_drvdata(dev);
- struct dev_pm_opp *opp;
+ struct opp *opp;
unsigned long freq = 0;
unsigned long voltage;
int err;
@@ -66,7 +66,6 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags)
/*
* Only update if there is a change of frequency
*/
- kbdev->current_freq = clk_get_rate(kbdev->clock);
if (kbdev->current_freq == freq) {
*target_freq = freq;
return 0;
@@ -117,7 +116,6 @@ kbase_devfreq_cur_freq(struct device *dev, unsigned long *freq)
{
struct kbase_device *kbdev = dev_get_drvdata(dev);
- kbdev->current_freq = clk_get_rate(kbdev->clock);
*freq = kbdev->current_freq;
return 0;
@@ -154,10 +152,10 @@ static int kbase_devfreq_init_freq_table(struct kbase_device *kbdev,
int count;
int i = 0;
unsigned long freq;
- struct dev_pm_opp *opp;
+ struct opp *opp;
rcu_read_lock();
- count = dev_pm_opp_get_opp_count(kbdev->dev);
+ count = opp_get_opp_count(kbdev->dev);
if (count < 0) {
rcu_read_unlock();
return count;
@@ -171,7 +169,7 @@ static int kbase_devfreq_init_freq_table(struct kbase_device *kbdev,
rcu_read_lock();
for (i = 0, freq = ULONG_MAX; i < count; i++, freq--) {
- opp = dev_pm_opp_find_freq_floor(kbdev->dev, &freq);
+ opp = opp_find_freq_floor(kbdev->dev, &freq);
if (IS_ERR(opp))
break;
@@ -3305,7 +3305,7 @@ static int power_control_init(struct platform_device *pdev)
}
#endif /* LINUX_VERSION_CODE >= 3, 12, 0 */
- kbdev->clock = clk_get(kbdev->dev, NULL);
+ kbdev->clock = clk_get(kbdev->dev, "clk_g3d");
if (IS_ERR_OR_NULL(kbdev->clock)) {
err = PTR_ERR(kbdev->clock);
kbdev->clock = NULL;
@@ -21,7 +21,17 @@
#include <mali_kbase.h>
#include <mali_kbase_defs.h>
#include <mali_kbase_config.h>
+#ifdef CONFIG_DEVFREQ_THERMAL
+#include <linux/devfreq_cooling.h>
+#endif
+
#include <trace/events/power.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))
+#include <linux/pm_opp.h>
+#else
+#include <linux/opp.h>
+#endif
+
#include <linux/pm_runtime.h>
#include <linux/clk.h>
#include <linux/regulator/consumer.h>
@@ -32,6 +42,9 @@
#include <backend/gpu/mali_kbase_pm_internal.h>
#include "mali_kbase_config_platform.h"
#include "mali_kbase_config_hifeatures.h"
+#ifdef CONFIG_HISI_IPA_THERMAL
+#include <linux/thermal.h>
+#endif
#define MALI_TRUE ((uint32_t)1)
#define MALI_FALSE ((uint32_t)0)
@@ -58,6 +71,10 @@ static struct kbase_io_resources io_resources = {
};
#endif /* CONFIG_OF */
+
+#define DEFAULT_POLLING_MS 20
+
+
#define RUNTIME_PM_DELAY_1MS 1
#define RUNTIME_PM_DELAY_30MS 30
@@ -158,6 +175,88 @@ static inline void kbase_platform_off(struct kbase_device *kbdev)
}
}
+#ifdef CONFIG_PM_DEVFREQ
+static int mali_kbase_devfreq_target(struct device *dev, unsigned long *_freq,
+ u32 flags)
+{
+ struct kbase_device *kbdev = (struct kbase_device *)dev->platform_data;
+ unsigned long old_freq = kbdev->devfreq->previous_freq;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))
+ struct dev_pm_opp *opp = NULL;
+#else
+ struct opp *opp = NULL;
+#endif
+ unsigned long freq;
+
+ rcu_read_lock();
+ opp = devfreq_recommended_opp(dev, _freq, flags);
+ if (IS_ERR(opp)) {
+ pr_err("[mali] Failed to get Operating Performance Point\n");
+ rcu_read_unlock();
+ return PTR_ERR(opp);
+ }
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))
+ freq = dev_pm_opp_get_freq(opp);
+#else
+ freq = opp_get_freq(opp);
+#endif
+ rcu_read_unlock();
+
+#ifdef CONFIG_HISI_IPA_THERMAL
+ freq = ipa_freq_limit(IPA_GPU,freq);
+#endif
+
+ if (old_freq == freq)
+ goto update_target;
+
+ trace_clock_set_rate("clk-g3d",freq,raw_smp_processor_id());
+
+ if (clk_set_rate((kbdev->clk), freq)) {
+ pr_err("[mali] Failed to set gpu freqency, [%lu->%lu]\n", old_freq, freq);
+ return -ENODEV;
+ }
+
+update_target:
+ *_freq = freq;
+
+ return 0;
+}
+
+static int mali_kbase_get_dev_status(struct device *dev,
+ struct devfreq_dev_status *stat)
+{
+ struct kbase_device *kbdev = (struct kbase_device *)dev->platform_data;
+
+ if (kbdev->pm.backend.metrics.kbdev != kbdev) {
+ pr_err("%s pm backend metrics not initialized\n", __func__);
+ return 0;
+ }
+
+ (void)kbase_pm_get_dvfs_action(kbdev);
+ stat->busy_time = kbdev->pm.backend.metrics.utilisation;
+ stat->total_time = 100;
+ stat->private_data = (void *)(long)kbdev->pm.backend.metrics.vsync_hit;
+ stat->current_frequency = clk_get_rate(kbdev->clk);
+
+#ifdef CONFIG_DEVFREQ_THERMAL
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,15)
+ memcpy(&kbdev->devfreq->last_status, stat, sizeof(*stat));
+#else
+ memcpy(&kbdev->devfreq_cooling->last_status, stat, sizeof(*stat));
+#endif
+#endif
+
+ return 0;
+}
+
+static struct devfreq_dev_profile mali_kbase_devfreq_profile = {
+ /* it would be abnormal to enable devfreq monitor during initialization. */
+ .polling_ms = DEFAULT_POLLING_MS, //STOP_POLLING,
+ .target = mali_kbase_devfreq_target,
+ .get_dev_status = mali_kbase_get_dev_status,
+};
+#endif
+
#ifdef CONFIG_REPORT_VSYNC
void mali_kbase_pm_report_vsync(int buffer_updated)
{
@@ -204,6 +303,120 @@ int kbase_platform_dvfs_enable(struct kbase_device *kbdev, bool enable, int freq
}
#endif
+#ifdef CONFIG_DEVFREQ_THERMAL
+static unsigned long hisi_model_static_power(unsigned long voltage)
+{
+ unsigned long temperature;
+ const unsigned long voltage_cubed = (voltage * voltage * voltage) >> 10;
+ unsigned long temp, temp_squared, temp_cubed;
+ unsigned long temp_scaling_factor = 0;
+
+ struct device_node *dev_node = NULL;
+ int ret = -EINVAL, i;
+ const char *temperature_scale_capacitance[5];
+ int capacitance[5] = {0};
+
+ dev_node = of_find_node_by_name(NULL, "capacitances");
+ if (dev_node) {
+ for (i = 0; i < 5; i++) {
+ ret = of_property_read_string_index(dev_node, "hisilicon,gpu_temp_scale_capacitance", i, &temperature_scale_capacitance[i]);
+ if (ret) {
+ pr_err("%s temperature_scale_capacitance [%d] read err\n",__func__,i);
+ continue;
+ }
+
+ ret = kstrtoint(temperature_scale_capacitance[i], 10, &capacitance[i]);
+ if (ret)
+ continue;
+ }
+ }
+
+ temperature = get_soc_temp();
+ temp = temperature / 1000;
+ temp_squared = temp * temp;
+ temp_cubed = temp_squared * temp;
+ temp_scaling_factor = capacitance[3] * temp_cubed +
+ capacitance[2] * temp_squared +
+ capacitance[1] * temp +
+ capacitance[0];
+
+ return (((capacitance[4] * voltage_cubed) >> 20) * temp_scaling_factor) / 1000000;/* [false alarm]: no problem - fortify check */
+}
+
+#ifdef CONFIG_HISI_THERMAL_SPM
+unsigned long hisi_calc_gpu_static_power(unsigned long voltage, unsigned long temperature)
+{
+ const long voltage_cubed = (voltage * voltage * voltage) >> 10;
+ long temp, temp_squared, temp_cubed;
+ long temp_scaling_factor;
+
+ struct device_node *dev_node = NULL;
+ int ret = -EINVAL, i;
+ const char *temperature_scale_capacitance[5];
+ int capacitance[5] = {0};
+
+ dev_node = of_find_node_by_name(NULL, "capacitances");
+ if (dev_node) {
+ for (i = 0; i < 5; i++) {
+ ret = of_property_read_string_index(dev_node, "hisilicon,gpu_temp_scale_capacitance", i, &temperature_scale_capacitance[i]);
+ if (ret) {
+ pr_err("%s temperature_scale_capacitance [%d] read err\n",__func__,i);
+ continue;
+ }
+
+ ret = kstrtoint(temperature_scale_capacitance[i], 10, &capacitance[i]);
+ if (ret)
+ continue;
+ }
+ }
+
+ temp = (long)temperature / 1000;
+ temp_squared = temp * temp;
+ temp_cubed = temp_squared * temp;
+ temp_scaling_factor = capacitance[3] * temp_cubed +
+ capacitance[2] * temp_squared +
+ capacitance[1] * temp +
+ capacitance[0];
+
+ return (unsigned long)(((((long)capacitance[4] * voltage_cubed) / (1024 * 1024)) * temp_scaling_factor) / 1000000);/* [false alarm]: no problem - fortify check */
+}
+EXPORT_SYMBOL(hisi_calc_gpu_static_power);
+#endif
+
+static unsigned long hisi_model_dynamic_power(unsigned long freq,
+ unsigned long voltage)
+{
+ /* The inputs: freq (f) is in Hz, and voltage (v) in mV.
+ * The coefficient (c) is in mW/(MHz mV mV).
+ *
+ * This function calculates the dynamic power after this formula:
+ * Pdyn (mW) = c (mW/(MHz*mV*mV)) * v (mV) * v (mV) * f (MHz)
+ */
+ const unsigned long v2 = (voltage * voltage) / 1000; /* m*(V*V) */
+ const unsigned long f_mhz = freq / 1000000; /* MHz */
+ unsigned long coefficient = 3600; /* mW/(MHz*mV*mV) */
+ struct device_node * dev_node = NULL;
+ u32 prop = 0;
+
+ dev_node = of_find_node_by_name(NULL, "capacitances");
+ if(dev_node)
+ {
+ int ret = of_property_read_u32(dev_node,"hisilicon,gpu_dyn_capacitance",&prop);
+ if(ret == 0)
+ {
+ coefficient = prop;
+ }
+ }
+
+ return (coefficient * v2 * f_mhz) / 1000000; /* mW */
+}
+
+static struct devfreq_cooling_ops hisi_model_ops = {
+ .get_static_power = hisi_model_static_power,
+ .get_dynamic_power = hisi_model_dynamic_power,
+};
+#endif
+
static int kbase_platform_init(struct kbase_device *kbdev)
{
int err;
@@ -214,11 +427,16 @@ static int kbase_platform_init(struct kbase_device *kbdev)
kbase_dev = kbdev;
#endif
+
+
return 1;
}
static void kbase_platform_term(struct kbase_device *kbdev)
{
+#ifdef CONFIG_PM_DEVFREQ
+ devfreq_remove_device(kbdev->devfreq);
+#endif
}
kbase_platform_funcs_conf platform_funcs = {
@@ -331,7 +549,9 @@ static void pm_callback_runtime_term(struct kbase_device *kbdev)
static void pm_callback_runtime_off(struct kbase_device *kbdev)
{
-#if defined(CONFIG_MALI_MIDGARD_DVFS)
+#ifdef CONFIG_PM_DEVFREQ
+ devfreq_suspend_device(kbdev->devfreq);
+#elif defined(CONFIG_MALI_MIDGARD_DVFS)
kbase_platform_dvfs_enable(kbdev, false, 0);
#endif
@@ -342,7 +562,9 @@ static int pm_callback_runtime_on(struct kbase_device *kbdev)
{
kbase_platform_on(kbdev);
-#if defined(CONFIG_MALI_MIDGARD_DVFS)
+#ifdef CONFIG_PM_DEVFREQ
+ devfreq_resume_device(kbdev->devfreq);
+#elif defined(CONFIG_MALI_MIDGARD_DVFS)
if (kbase_platform_dvfs_enable(kbdev, true, 0) != MALI_TRUE)
return -EPERM;
#endif
@@ -1,32 +1,38 @@
/*
- * Device driver for Hi6421 PMIC
+ * Device driver for Hi6421 IC
*
* Copyright (c) <2011-2014> HiSilicon Technologies Co., Ltd.
* http://www.hisilicon.com
- * Copyright (c) <2013-2017> Linaro Ltd.
+ * Copyright (c) <2013-2014> Linaro Ltd.
* http://www.linaro.org
*
* Author: Guodong Xu <guodong.xu@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/mfd/core.h>
-#include <linux/mfd/hi6421-pmic.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/mfd/hi6421-pmic.h>
static const struct mfd_cell hi6421_devs[] = {
{ .name = "hi6421-regulator", },
-};
-
-static const struct mfd_cell hi6421v530_devs[] = {
{ .name = "hi6421v530-regulator", },
};
@@ -37,33 +43,12 @@ static const struct regmap_config hi6421_regmap_config = {
.max_register = HI6421_REG_TO_BUS_ADDR(HI6421_REG_MAX),
};
-static const struct of_device_id of_hi6421_pmic_match[] = {
- {
- .compatible = "hisilicon,hi6421-pmic",
- .data = (void *)HI6421
- },
- {
- .compatible = "hisilicon,hi6421v530-pmic",
- .data = (void *)HI6421_V530
- },
- { },
-};
-MODULE_DEVICE_TABLE(of, of_hi6421_pmic_match);
-
static int hi6421_pmic_probe(struct platform_device *pdev)
{
struct hi6421_pmic *pmic;
struct resource *res;
- const struct of_device_id *id;
- const struct mfd_cell *subdevs;
- enum hi6421_type type;
void __iomem *base;
- int n_subdevs, ret;
-
- id = of_match_device(of_hi6421_pmic_match, &pdev->dev);
- if (!id)
- return -EINVAL;
- type = (enum hi6421_type)id->data;
+ int ret;
pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic)
@@ -77,50 +62,43 @@ static int hi6421_pmic_probe(struct platform_device *pdev)
pmic->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
&hi6421_regmap_config);
if (IS_ERR(pmic->regmap)) {
- dev_err(&pdev->dev, "Failed to initialise Regmap: %ld\n",
- PTR_ERR(pmic->regmap));
+ dev_err(&pdev->dev,
+ "regmap init failed: %ld\n", PTR_ERR(pmic->regmap));
return PTR_ERR(pmic->regmap);
}
- platform_set_drvdata(pdev, pmic);
-
- switch (type) {
- case HI6421:
- /* set over-current protection debounce 8ms */
- regmap_update_bits(pmic->regmap, HI6421_OCP_DEB_CTRL_REG,
+#ifdef CONFIG_REGULATOR_HI6421
+ /* set over-current protection debounce 8ms */
+ regmap_update_bits(pmic->regmap, HI6421_OCP_DEB_CTRL_REG,
(HI6421_OCP_DEB_SEL_MASK
| HI6421_OCP_EN_DEBOUNCE_MASK
| HI6421_OCP_AUTO_STOP_MASK),
(HI6421_OCP_DEB_SEL_8MS
| HI6421_OCP_EN_DEBOUNCE_ENABLE));
+#endif
- subdevs = hi6421_devs;
- n_subdevs = ARRAY_SIZE(hi6421_devs);
- break;
- case HI6421_V530:
- subdevs = hi6421v530_devs;
- n_subdevs = ARRAY_SIZE(hi6421v530_devs);
- break;
- default:
- dev_err(&pdev->dev, "Unknown device type %d\n",
- (unsigned int)type);
- return -EINVAL;
- }
+ platform_set_drvdata(pdev, pmic);
- ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE,
- subdevs, n_subdevs, NULL, 0, NULL);
+ ret = devm_mfd_add_devices(&pdev->dev, 0, hi6421_devs,
+ ARRAY_SIZE(hi6421_devs), NULL, 0, NULL);
if (ret) {
- dev_err(&pdev->dev, "Failed to add child devices: %d\n", ret);
+ dev_err(&pdev->dev, "add mfd devices failed: %d\n", ret);
return ret;
}
return 0;
}
+static const struct of_device_id of_hi6421_pmic_match_tbl[] = {
+ { .compatible = "hisilicon,hi6421-pmic", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, of_hi6421_pmic_match_tbl);
+
static struct platform_driver hi6421_pmic_driver = {
.driver = {
- .name = "hi6421_pmic",
- .of_match_table = of_hi6421_pmic_match,
+ .name = "hi6421_pmic",
+ .of_match_table = of_hi6421_pmic_match_tbl,
},
.probe = hi6421_pmic_probe,
};
@@ -274,7 +274,7 @@ config REGULATOR_HI6421V530
tristate "HiSilicon Hi6421v530 PMIC voltage regulator support"
depends on MFD_HI6421_PMIC && OF
help
- This driver provides support for the voltage regulators on
+ This driver provides support for the voltage regulators on the
HiSilicon Hi6421v530 PMU / Codec IC.
Hi6421v530 is a multi-function device which, on regulator part,
provides 5 general purpose LDOs, and all of them come with support
@@ -621,14 +621,7 @@ static int hi6421_regulator_probe(struct platform_device *pdev)
return 0;
}
-static const struct platform_device_id hi6421_regulator_table[] = {
- { .name = "hi6421-regulator" },
- {},
-};
-MODULE_DEVICE_TABLE(platform, hi6421_regulator_table);
-
static struct platform_driver hi6421_regulator_driver = {
- .id_table = hi6421_regulator_table,
.driver = {
.name = "hi6421-regulator",
},
@@ -1,25 +1,39 @@
/*
* Device driver for regulators in Hi6421V530 IC
*
- * Copyright (c) <2017> HiSilicon Technologies Co., Ltd.
+ * Copyright (c) <2014-2017> HiSilicon Technologies Co., Ltd.
* http://www.hisilicon.com
- * Copyright (c) <2017> Linaro Ltd.
+ * Copyright (c) <2013-2014> Linaro Ltd.
* http://www.linaro.org
*
* Author: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
- * Guodong Xu <guodong.xu@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-#include <linux/mfd/hi6421-pmic.h>
+#include <linux/slab.h>
+#include <linux/device.h>
#include <linux/module.h>
-#include <linux/of.h>
+#include <linux/err.h>
#include <linux/platform_device.h>
+#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/mfd/hi6421-pmic.h>
+#include <linux/io.h>
+
+/*
+ * struct hi6421c530_regulator_pdata - Hi6421V530 regulator data
+ * of platform device.
+ * @lock: mutex to serialize regulator enable
+ */
+struct hi6421v530_regulator_pdata {
+ struct mutex lock;
+};
/*
* struct hi6421v530_regulator_info - hi6421v530 regulator information
@@ -28,9 +42,9 @@
* @eco_microamp: eco mode load upper limit (in uA), valid for LDOs only
*/
struct hi6421v530_regulator_info {
- struct regulator_desc rdesc;
- u8 mode_mask;
- u32 eco_microamp;
+ struct regulator_desc desc;
+ u8 mode_mask;
+ u32 eco_microamp;
};
/* HI6421v530 regulators */
@@ -40,6 +54,21 @@ enum hi6421v530_regulator_id {
HI6421V530_LDO11,
HI6421V530_LDO15,
HI6421V530_LDO16,
+ HI6421V530_NUM_REGULATORS,
+};
+
+#define HI6421V530_REGULATOR_OF_MATCH(_name, id) \
+{ \
+ .name = #_name, \
+ .driver_data = (void *) HI6421V530_##id, \
+}
+
+static struct of_regulator_match hi6421v530_regulator_match[] = {
+ HI6421V530_REGULATOR_OF_MATCH(hi6421v530_ldo3, LDO3),
+ HI6421V530_REGULATOR_OF_MATCH(hi6421v530_ldo9, LDO9),
+ HI6421V530_REGULATOR_OF_MATCH(hi6421v530_ldo11, LDO11),
+ HI6421V530_REGULATOR_OF_MATCH(hi6421v530_ldo15, LDO15),
+ HI6421V530_REGULATOR_OF_MATCH(hi6421v530_ldo16, LDO16),
};
static const unsigned int ldo_3_voltages[] = {
@@ -74,32 +103,32 @@ static const struct regulator_ops hi6421v530_ldo_ops;
* ecomask - eco mode mask
* ecoamp - eco mode load uppler limit in uA
*/
-#define HI6421V530_LDO(_ID, v_table, vreg, vmask, ereg, emask, \
- odelay, ecomask, ecoamp) { \
- .rdesc = { \
- .name = #_ID, \
- .of_match = of_match_ptr(#_ID), \
- .regulators_node = of_match_ptr("regulators"), \
- .ops = &hi6421v530_ldo_ops, \
- .type = REGULATOR_VOLTAGE, \
- .id = HI6421V530_##_ID, \
- .owner = THIS_MODULE, \
- .n_voltages = ARRAY_SIZE(v_table), \
- .volt_table = v_table, \
- .vsel_reg = HI6421_REG_TO_BUS_ADDR(vreg), \
- .vsel_mask = vmask, \
- .enable_reg = HI6421_REG_TO_BUS_ADDR(ereg), \
- .enable_mask = emask, \
- .enable_time = HI6421V530_LDO_ENABLE_TIME, \
- .off_on_delay = odelay, \
- }, \
- .mode_mask = ecomask, \
- .eco_microamp = ecoamp, \
-}
+#define HI6421V530_LDO(_id, v_table, vreg, vmask, ereg, emask, \
+ odelay, ecomask, ecoamp) \
+ [HI6421V530_##_id] = { \
+ .desc = { \
+ .name = #_id, \
+ .ops = &hi6421v530_ldo_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = HI6421V530_##_id, \
+ .owner = THIS_MODULE, \
+ .n_voltages = ARRAY_SIZE(v_table), \
+ .volt_table = v_table, \
+ .vsel_reg = HI6421_REG_TO_BUS_ADDR(vreg), \
+ .vsel_mask = vmask, \
+ .enable_reg = HI6421_REG_TO_BUS_ADDR(ereg), \
+ .enable_mask = emask, \
+ .enable_time = HI6421V530_LDO_ENABLE_TIME, \
+ .off_on_delay = odelay, \
+ }, \
+ .mode_mask = ecomask, \
+ .eco_microamp = ecoamp, \
+ }
/* HI6421V530 regulator information */
-static struct hi6421v530_regulator_info hi6421v530_regulator_info[] = {
+static struct hi6421v530_regulator_info
+ hi6421v530_regulator_info[HI6421V530_NUM_REGULATORS] = {
HI6421V530_LDO(LDO3, ldo_3_voltages, 0x061, 0xf, 0x060, 0x2,
20000, 0x6, 8000),
HI6421V530_LDO(LDO9, ldo_9_11_voltages, 0x06b, 0x7, 0x06a, 0x2,
@@ -112,6 +141,76 @@ static struct hi6421v530_regulator_info hi6421v530_regulator_info[] = {
40000, 0x6, 8000),
};
+static int hi6421v530_regulator_enable(struct regulator_dev *rdev)
+{
+ struct hi6421v530_regulator_pdata *pdata;
+ int ret = 0;
+
+ pdata = dev_get_drvdata(rdev->dev.parent);
+ mutex_lock(&pdata->lock);
+
+ ret = regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
+ rdev->desc->enable_mask,
+ 1 << (ffs(rdev->desc->enable_mask) - 1));
+
+ mutex_unlock(&pdata->lock);
+ return ret;
+}
+
+static int hi6421v530_regulator_disable(struct regulator_dev *rdev)
+{
+ struct hi6421v530_regulator_pdata *pdata;
+ int ret = 0;
+
+ pdata = dev_get_drvdata(rdev->dev.parent);
+ mutex_lock(&pdata->lock);
+
+ ret = regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
+ rdev->desc->enable_mask, 0);
+
+ mutex_unlock(&pdata->lock);
+ return ret;
+}
+
+static int hi6421v530_regulator_is_enabled(struct regulator_dev *rdev)
+{
+ unsigned int reg_val = 0;
+ int ret = 0;
+
+ regmap_read(rdev->regmap, rdev->desc->enable_reg, ®_val);
+
+ ret = (reg_val & (rdev->desc->enable_mask)) ? 1 : 0;
+ return ret;
+}
+
+static int hi6421v530_regulator_set_voltage(struct regulator_dev *rdev,
+ unsigned int sel)
+{
+ struct hi6421v530_regulator_pdata *pdata;
+ int ret = 0;
+
+ pdata = dev_get_drvdata(rdev->dev.parent);
+ mutex_lock(&pdata->lock);
+
+ ret = regmap_update_bits(rdev->regmap, rdev->desc->vsel_reg,
+ rdev->desc->vsel_mask,
+ sel << (ffs(rdev->desc->vsel_mask) - 1));
+
+ mutex_unlock(&pdata->lock);
+ return ret;
+}
+
+static int hi6421v530_regulator_get_voltage(struct regulator_dev *rdev)
+{
+ unsigned int reg_val = 0;
+ int voltage;
+
+ regmap_read(rdev->regmap, rdev->desc->vsel_reg, ®_val);
+
+ voltage = reg_val >> (ffs(rdev->desc->vsel_mask) - 1);
+ return voltage;
+}
+
static unsigned int hi6421v530_regulator_ldo_get_mode(
struct regulator_dev *rdev)
{
@@ -131,9 +230,11 @@ static int hi6421v530_regulator_ldo_set_mode(struct regulator_dev *rdev,
unsigned int mode)
{
struct hi6421v530_regulator_info *info;
+ struct hi6421v530_regulator_pdata *pdata;
unsigned int new_mode;
info = rdev_get_drvdata(rdev);
+ pdata = dev_get_drvdata(rdev->dev.parent);
switch (mode) {
case REGULATOR_MODE_NORMAL:
new_mode = 0;
@@ -145,63 +246,103 @@ static int hi6421v530_regulator_ldo_set_mode(struct regulator_dev *rdev,
return -EINVAL;
}
+ mutex_lock(&pdata->lock);
regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
info->mode_mask, new_mode);
+ mutex_unlock(&pdata->lock);
return 0;
}
static const struct regulator_ops hi6421v530_ldo_ops = {
- .is_enabled = regulator_is_enabled_regmap,
- .enable = regulator_enable_regmap,
- .disable = regulator_disable_regmap,
+ .is_enabled = hi6421v530_regulator_is_enabled,
+ .enable = hi6421v530_regulator_enable,
+ .disable = hi6421v530_regulator_disable,
.list_voltage = regulator_list_voltage_table,
.map_voltage = regulator_map_voltage_ascend,
- .get_voltage_sel = regulator_get_voltage_sel_regmap,
- .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .get_voltage_sel = hi6421v530_regulator_get_voltage,
+ .set_voltage_sel = hi6421v530_regulator_set_voltage,
.get_mode = hi6421v530_regulator_ldo_get_mode,
.set_mode = hi6421v530_regulator_ldo_set_mode,
};
+static int hi6421v530_regulator_register(struct platform_device *pdev,
+ struct regmap *rmap,
+ struct regulator_init_data *init_data,
+ int id, struct device_node *np)
+{
+ struct hi6421v530_regulator_info *info = NULL;
+ struct regulator_config config = { };
+ struct regulator_dev *rdev;
+
+ /* assign per-regulator data */
+ info = &hi6421v530_regulator_info[id];
+
+ config.dev = &pdev->dev;
+ config.init_data = init_data;
+ config.driver_data = info;
+ config.regmap = rmap;
+ config.of_node = np;
+
+ /* register regulator with framework */
+ rdev = devm_regulator_register(&pdev->dev, &info->desc, &config);
+ if (IS_ERR(rdev)) {
+ dev_err(&pdev->dev, "failed to register regulator %s\n",
+ info->desc.name);
+ return PTR_ERR(rdev);
+ }
+
+ rdev->constraints->valid_modes_mask = info->mode_mask;
+ rdev->constraints->valid_ops_mask |=
+ REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE;
+
+ return 0;
+}
+
static int hi6421v530_regulator_probe(struct platform_device *pdev)
{
+ struct device *dev = &pdev->dev;
+ struct device_node *np;
struct hi6421_pmic *pmic;
- struct regulator_dev *rdev;
- struct regulator_config config = { };
- unsigned int i;
+ struct hi6421v530_regulator_pdata *pdata;
+ int i, ret = 0;
- pmic = dev_get_drvdata(pdev->dev.parent);
- if (!pmic) {
- dev_err(&pdev->dev, "no pmic in the regulator parent node\n");
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+ mutex_init(&pdata->lock);
+
+ platform_set_drvdata(pdev, pdata);
+
+ np = of_get_child_by_name(dev->parent->of_node, "regulators");
+ if (!np)
return -ENODEV;
+
+ ret = of_regulator_match(dev, np,
+ hi6421v530_regulator_match,
+ ARRAY_SIZE(hi6421v530_regulator_match));
+ of_node_put(np);
+ if (ret < 0) {
+ dev_err(dev, "Error parsing regulator init data: %d\n", ret);
+ return ret;
}
- for (i = 0; i < ARRAY_SIZE(hi6421v530_regulator_info); i++) {
- config.dev = pdev->dev.parent;
- config.regmap = pmic->regmap;
- config.driver_data = &hi6421v530_regulator_info[i];
-
- rdev = devm_regulator_register(&pdev->dev,
- &hi6421v530_regulator_info[i].rdesc,
- &config);
- if (IS_ERR(rdev)) {
- dev_err(&pdev->dev, "failed to register regulator %s\n",
- hi6421v530_regulator_info[i].rdesc.name);
- return PTR_ERR(rdev);
- }
+ pmic = dev_get_drvdata(dev->parent);
+
+ for (i = 0; i < ARRAY_SIZE(hi6421v530_regulator_match); i++) {
+ ret = hi6421v530_regulator_register(pdev, pmic->regmap,
+ hi6421v530_regulator_match[i].init_data, i,
+ hi6421v530_regulator_match[i].of_node);
+
+ if (ret)
+ return ret;
}
+
return 0;
}
-static const struct platform_device_id hi6421v530_regulator_table[] = {
- { .name = "hi6421v530-regulator" },
- {},
-};
-MODULE_DEVICE_TABLE(platform, hi6421v530_regulator_table);
-
static struct platform_driver hi6421v530_regulator_driver = {
- .id_table = hi6421v530_regulator_table,
.driver = {
.name = "hi6421v530-regulator",
},
reverted a bunch of stuff to get things booting to graphics. Cc: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org> --- arch/arm64/boot/dts/hisilicon/hi3660-gpu.dtsi | 47 +- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 396 ++++++----- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 773 ++++++++++++--------- .../arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | 687 +++++------------- arch/arm64/configs/defconfig | 18 +- arch/arm64/configs/hikey960_defconfig | 40 -- .../gpu/arm_gpu/backend/gpu/mali_kbase_devfreq.c | 10 +- drivers/gpu/arm_gpu/mali_kbase_core_linux.c | 2 +- .../hisilicon/mali_kbase_config_hisilicon.c | 226 +++++- drivers/mfd/hi6421-pmic-core.c | 90 +-- drivers/regulator/Kconfig | 2 +- drivers/regulator/hi6421-regulator.c | 7 - drivers/regulator/hi6421v530-regulator.c | 265 +++++-- 13 files changed, 1293 insertions(+), 1270 deletions(-) mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi -- 2.7.4