| Message ID | 20250530092850.631831-3-quic_wasimn@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | qcom: Add support for IQ-9075-evk board | expand |
On Fri, May 30, 2025 at 02:58:45PM +0530, Wasim Nazir wrote: > From: Pratyush Brahma <quic_pbrahma@quicinc.com> > > SA8775P has a memory map which caters to the auto specific requirements. I thought SA8775P was the IoT platform and SA8255P was the automotive one. Has this changed? > QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which > inherit the memory map of SA8775P require a slightly different memory > map as compared to SA8775P auto parts. > This new memory map is applicable for all the IoT boards which inherit > the initial SA8775P memory map. This is not applicable for non-IoT Is there are platform out there that actually uses the "initial SA8775P memory map"? > boards. > > Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been > introduced as part of firmware updates for IoT. The size and base address > have been updated for video PIL carveout compared to SA8775P since it is > being brought up for the first time on IoT boards. The base addresses > of the rest of the PIL carveouts have been updated to accommodate the > change in size of video since PIL regions are relocatable and their > functionality is not impacted due to this change. The size of camera > pil has also been increased without breaking any feature. > > The size of trusted apps carveout has also been reduced since it is > sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem > carveout and its corresponding scm reference has been removed as these > are not required for IoT parts. > > Incorporate these changes in the updated memory map. > > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> > Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com> > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com> > --- > .../boot/dts/qcom/iq9-reserved-memory.dtsi | 113 ++++++++++++++++++ > 1 file changed, 113 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi > new file mode 100644 > index 000000000000..ff2600eb5e3d > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi The naming convention is <soc>-<something>.dtsi and I don't see any other uses of the "iq9" naming. > @@ -0,0 +1,113 @@ > +// SPDX-License-Identifier: BSD-3-Clause > + Why is there a blank space here? Regards, Bjorn > +/* > + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +/delete-node/ &pil_camera_mem; > +/delete-node/ &pil_adsp_mem; > +/delete-node/ &pil_gdsp0_mem; > +/delete-node/ &pil_gdsp1_mem; > +/delete-node/ &pil_cdsp0_mem; > +/delete-node/ &pil_gpu_mem; > +/delete-node/ &pil_cdsp1_mem; > +/delete-node/ &pil_cvp_mem; > +/delete-node/ &pil_video_mem; > +/delete-node/ &audio_mdf_mem; > +/delete-node/ &trusted_apps_mem; > +/delete-node/ &hyptz_reserved_mem; > +/delete-node/ &tz_ffi_mem; > + > +/ { > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + gunyah_md_mem: gunyah-md@91a80000 { > + reg = <0x0 0x91a80000 0x0 0x80000>; > + no-map; > + }; > + > + pil_camera_mem: pil-camera@95200000 { > + reg = <0x0 0x95200000 0x0 0x700000>; > + no-map; > + }; > + > + pil_adsp_mem: pil-adsp@95900000 { > + reg = <0x0 0x95900000 0x0 0x1e00000>; > + no-map; > + }; > + > + q6_adsp_dtb_mem: q6-adsp-dtb@97700000 { > + reg = <0x0 0x97700000 0x0 0x80000>; > + no-map; > + }; > + > + q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 { > + reg = <0x0 0x97780000 0x0 0x80000>; > + no-map; > + }; > + > + pil_gdsp0_mem: pil-gdsp0@97800000 { > + reg = <0x0 0x97800000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_gdsp1_mem: pil-gdsp1@99600000 { > + reg = <0x0 0x99600000 0x0 0x1e00000>; > + no-map; > + }; > + > + q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 { > + reg = <0x0 0x9b400000 0x0 0x80000>; > + no-map; > + }; > + > + q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 { > + reg = <0x0 0x9b480000 0x0 0x80000>; > + no-map; > + }; > + > + pil_cdsp0_mem: pil-cdsp0@9b500000 { > + reg = <0x0 0x9b500000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_gpu_mem: pil-gpu@9d300000 { > + reg = <0x0 0x9d300000 0x0 0x2000>; > + no-map; > + }; > + > + q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 { > + reg = <0x0 0x9d380000 0x0 0x80000>; > + no-map; > + }; > + > + pil_cdsp1_mem: pil-cdsp1@9d400000 { > + reg = <0x0 0x9d400000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_cvp_mem: pil-cvp@9f200000 { > + reg = <0x0 0x9f200000 0x0 0x700000>; > + no-map; > + }; > + > + pil_video_mem: pil-video@9f900000 { > + reg = <0x0 0x9f900000 0x0 0x1000000>; > + no-map; > + }; > + > + trusted_apps_mem: trusted-apps@d1900000 { > + reg = <0x0 0xd1900000 0x0 0x1c00000>; > + no-map; > + }; > + }; > + > + firmware { > + scm { > + /delete-property/ memory-region; > + }; > + }; > +}; > -- > 2.49.0 >
On Mon, Jun 02, 2025 at 10:41:39AM -0500, Bjorn Andersson wrote: > On Fri, May 30, 2025 at 02:58:45PM +0530, Wasim Nazir wrote: > > From: Pratyush Brahma <quic_pbrahma@quicinc.com> > > > > SA8775P has a memory map which caters to the auto specific requirements. > > I thought SA8775P was the IoT platform and SA8255P was the automotive > one. Has this changed? Both SA8775P & SA8255P is for auto but former one is non-SCMI based while the later one is SCMI based chip. Only IQ9 series of chips (QCS9100 & QCS9075) are for IOT. > > > QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which > > inherit the memory map of SA8775P require a slightly different memory > > map as compared to SA8775P auto parts. > > This new memory map is applicable for all the IoT boards which inherit > > the initial SA8775P memory map. This is not applicable for non-IoT > > Is there are platform out there that actually uses the "initial SA8775P > memory map"? Yes currently sa8775p-ride and sa8775p-ride-r3 are using initial memory map. > > > boards. > > > > Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been > > introduced as part of firmware updates for IoT. The size and base address > > have been updated for video PIL carveout compared to SA8775P since it is > > being brought up for the first time on IoT boards. The base addresses > > of the rest of the PIL carveouts have been updated to accommodate the > > change in size of video since PIL regions are relocatable and their > > functionality is not impacted due to this change. The size of camera > > pil has also been increased without breaking any feature. > > > > The size of trusted apps carveout has also been reduced since it is > > sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem > > carveout and its corresponding scm reference has been removed as these > > are not required for IoT parts. > > > > Incorporate these changes in the updated memory map. > > > > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> > > Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com> > > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com> > > --- > > .../boot/dts/qcom/iq9-reserved-memory.dtsi | 113 ++++++++++++++++++ > > 1 file changed, 113 insertions(+) > > create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi > > > > diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi > > new file mode 100644 > > index 000000000000..ff2600eb5e3d > > --- /dev/null > > +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi > > The naming convention is <soc>-<something>.dtsi and I don't see any > other uses of the "iq9" naming. As this new memory map is common for IQ9 series of SoC (QCS9100 & QCS9075), so we have used its common name. Once the DT structure for QCS9100 is refactored, we would update this common file there. > > > @@ -0,0 +1,113 @@ > > +// SPDX-License-Identifier: BSD-3-Clause > > + > > Why is there a blank space here? Will remove this in next patch. > > Regards, > Bjorn Regards, Wasim > > > +/* > > + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. > > + */ > > + > > +/delete-node/ &pil_camera_mem; > > +/delete-node/ &pil_adsp_mem; > > +/delete-node/ &pil_gdsp0_mem; > > +/delete-node/ &pil_gdsp1_mem; > > +/delete-node/ &pil_cdsp0_mem; > > +/delete-node/ &pil_gpu_mem; > > +/delete-node/ &pil_cdsp1_mem; > > +/delete-node/ &pil_cvp_mem; > > +/delete-node/ &pil_video_mem; > > +/delete-node/ &audio_mdf_mem; > > +/delete-node/ &trusted_apps_mem; > > +/delete-node/ &hyptz_reserved_mem; > > +/delete-node/ &tz_ffi_mem; > > + > > +/ { > > + reserved-memory { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + gunyah_md_mem: gunyah-md@91a80000 { > > + reg = <0x0 0x91a80000 0x0 0x80000>; > > + no-map; > > + }; > > + > > + pil_camera_mem: pil-camera@95200000 { > > + reg = <0x0 0x95200000 0x0 0x700000>; > > + no-map; > > + }; > > + > > + pil_adsp_mem: pil-adsp@95900000 { > > + reg = <0x0 0x95900000 0x0 0x1e00000>; > > + no-map; > > + }; > > + > > + q6_adsp_dtb_mem: q6-adsp-dtb@97700000 { > > + reg = <0x0 0x97700000 0x0 0x80000>; > > + no-map; > > + }; > > + > > + q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 { > > + reg = <0x0 0x97780000 0x0 0x80000>; > > + no-map; > > + }; > > + > > + pil_gdsp0_mem: pil-gdsp0@97800000 { > > + reg = <0x0 0x97800000 0x0 0x1e00000>; > > + no-map; > > + }; > > + > > + pil_gdsp1_mem: pil-gdsp1@99600000 { > > + reg = <0x0 0x99600000 0x0 0x1e00000>; > > + no-map; > > + }; > > + > > + q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 { > > + reg = <0x0 0x9b400000 0x0 0x80000>; > > + no-map; > > + }; > > + > > + q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 { > > + reg = <0x0 0x9b480000 0x0 0x80000>; > > + no-map; > > + }; > > + > > + pil_cdsp0_mem: pil-cdsp0@9b500000 { > > + reg = <0x0 0x9b500000 0x0 0x1e00000>; > > + no-map; > > + }; > > + > > + pil_gpu_mem: pil-gpu@9d300000 { > > + reg = <0x0 0x9d300000 0x0 0x2000>; > > + no-map; > > + }; > > + > > + q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 { > > + reg = <0x0 0x9d380000 0x0 0x80000>; > > + no-map; > > + }; > > + > > + pil_cdsp1_mem: pil-cdsp1@9d400000 { > > + reg = <0x0 0x9d400000 0x0 0x1e00000>; > > + no-map; > > + }; > > + > > + pil_cvp_mem: pil-cvp@9f200000 { > > + reg = <0x0 0x9f200000 0x0 0x700000>; > > + no-map; > > + }; > > + > > + pil_video_mem: pil-video@9f900000 { > > + reg = <0x0 0x9f900000 0x0 0x1000000>; > > + no-map; > > + }; > > + > > + trusted_apps_mem: trusted-apps@d1900000 { > > + reg = <0x0 0xd1900000 0x0 0x1c00000>; > > + no-map; > > + }; > > + }; > > + > > + firmware { > > + scm { > > + /delete-property/ memory-region; > > + }; > > + }; > > +}; > > -- > > 2.49.0 > >
On Wed, Jun 04, 2025 at 03:05:55PM +0530, Wasim Nazir wrote: > On Mon, Jun 02, 2025 at 10:41:39AM -0500, Bjorn Andersson wrote: > > On Fri, May 30, 2025 at 02:58:45PM +0530, Wasim Nazir wrote: > > > From: Pratyush Brahma <quic_pbrahma@quicinc.com> > > > > > > SA8775P has a memory map which caters to the auto specific requirements. > > > > I thought SA8775P was the IoT platform and SA8255P was the automotive > > one. Has this changed? > > Both SA8775P & SA8255P is for auto but former one is non-SCMI based while > the later one is SCMI based chip. > > Only IQ9 series of chips (QCS9100 & QCS9075) are for IOT. > > > > > > QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which > > > inherit the memory map of SA8775P require a slightly different memory > > > map as compared to SA8775P auto parts. > > > This new memory map is applicable for all the IoT boards which inherit > > > the initial SA8775P memory map. This is not applicable for non-IoT > > > > Is there are platform out there that actually uses the "initial SA8775P > > memory map"? > > Yes currently sa8775p-ride and sa8775p-ride-r3 are using initial memory > map. > > > > > > boards. > > > > > > Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been > > > introduced as part of firmware updates for IoT. The size and base address > > > have been updated for video PIL carveout compared to SA8775P since it is > > > being brought up for the first time on IoT boards. The base addresses > > > of the rest of the PIL carveouts have been updated to accommodate the > > > change in size of video since PIL regions are relocatable and their > > > functionality is not impacted due to this change. The size of camera > > > pil has also been increased without breaking any feature. > > > > > > The size of trusted apps carveout has also been reduced since it is > > > sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem > > > carveout and its corresponding scm reference has been removed as these > > > are not required for IoT parts. > > > > > > Incorporate these changes in the updated memory map. > > > > > > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> > > > Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com> > > > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com> > > > --- > > > .../boot/dts/qcom/iq9-reserved-memory.dtsi | 113 ++++++++++++++++++ > > > 1 file changed, 113 insertions(+) > > > create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi > > > > > > diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi > > > new file mode 100644 > > > index 000000000000..ff2600eb5e3d > > > --- /dev/null > > > +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi > > > > The naming convention is <soc>-<something>.dtsi and I don't see any > > other uses of the "iq9" naming. > > As this new memory map is common for IQ9 series of SoC (QCS9100 & > QCS9075), so we have used its common name. IQ9 name is not known or visible outside of this commit. > Once the DT structure for QCS9100 is refactored, we would update this > common file there. Can you refactor it first? > > >
On Wed, Jun 04, 2025 at 04:21:46PM +0300, Dmitry Baryshkov wrote: > On Wed, Jun 04, 2025 at 03:05:55PM +0530, Wasim Nazir wrote: > > On Mon, Jun 02, 2025 at 10:41:39AM -0500, Bjorn Andersson wrote: > > > On Fri, May 30, 2025 at 02:58:45PM +0530, Wasim Nazir wrote: > > > > From: Pratyush Brahma <quic_pbrahma@quicinc.com> > > > > > > > > SA8775P has a memory map which caters to the auto specific requirements. > > > > > > I thought SA8775P was the IoT platform and SA8255P was the automotive > > > one. Has this changed? > > > > Both SA8775P & SA8255P is for auto but former one is non-SCMI based while > > the later one is SCMI based chip. > > > > Only IQ9 series of chips (QCS9100 & QCS9075) are for IOT. > > > > > > > > > QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which > > > > inherit the memory map of SA8775P require a slightly different memory > > > > map as compared to SA8775P auto parts. > > > > This new memory map is applicable for all the IoT boards which inherit > > > > the initial SA8775P memory map. This is not applicable for non-IoT > > > > > > Is there are platform out there that actually uses the "initial SA8775P > > > memory map"? > > > > Yes currently sa8775p-ride and sa8775p-ride-r3 are using initial memory > > map. > > > > > > > > > boards. > > > > > > > > Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been > > > > introduced as part of firmware updates for IoT. The size and base address > > > > have been updated for video PIL carveout compared to SA8775P since it is > > > > being brought up for the first time on IoT boards. The base addresses > > > > of the rest of the PIL carveouts have been updated to accommodate the > > > > change in size of video since PIL regions are relocatable and their > > > > functionality is not impacted due to this change. The size of camera > > > > pil has also been increased without breaking any feature. > > > > > > > > The size of trusted apps carveout has also been reduced since it is > > > > sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem > > > > carveout and its corresponding scm reference has been removed as these > > > > are not required for IoT parts. > > > > > > > > Incorporate these changes in the updated memory map. > > > > > > > > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> > > > > Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com> > > > > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com> > > > > --- > > > > .../boot/dts/qcom/iq9-reserved-memory.dtsi | 113 ++++++++++++++++++ > > > > 1 file changed, 113 insertions(+) > > > > create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi > > > > > > > > diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi > > > > new file mode 100644 > > > > index 000000000000..ff2600eb5e3d > > > > --- /dev/null > > > > +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi > > > > > > The naming convention is <soc>-<something>.dtsi and I don't see any > > > other uses of the "iq9" naming. > > > > As this new memory map is common for IQ9 series of SoC (QCS9100 & > > QCS9075), so we have used its common name. > > IQ9 name is not known or visible outside of this commit. Are you referring to add the same in cover-letter? > > > Once the DT structure for QCS9100 is refactored, we would update this > > common file there. > > Can you refactor it first? This refactoring involves changes in all the ride/ride-r3 boards which are based on sa8775p & qcs9100. Even though we had sent v0[1] but we still need to conclude on the final structure. Since, ethernet is broken in upstream, we are working on its fix before sending another series. Hence, we want to proceed for iq9075-evk for now and once qcs9100 is finalized, we can use the memory-map there. But to avoid this dependency and to proceed with iq9075-evk alone, I can rename it to qcs9075-reserved-memory.dtsi. Let me know if that works here. [1] https://lore.kernel.org/all/20250507065116.353114-1-quic_wasimn@quicinc.com/ > > > > > > > > -- > With best wishes > Dmitry Regards, Wasim
diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi new file mode 100644 index 000000000000..ff2600eb5e3d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/delete-node/ &pil_camera_mem; +/delete-node/ &pil_adsp_mem; +/delete-node/ &pil_gdsp0_mem; +/delete-node/ &pil_gdsp1_mem; +/delete-node/ &pil_cdsp0_mem; +/delete-node/ &pil_gpu_mem; +/delete-node/ &pil_cdsp1_mem; +/delete-node/ &pil_cvp_mem; +/delete-node/ &pil_video_mem; +/delete-node/ &audio_mdf_mem; +/delete-node/ &trusted_apps_mem; +/delete-node/ &hyptz_reserved_mem; +/delete-node/ &tz_ffi_mem; + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_md_mem: gunyah-md@91a80000 { + reg = <0x0 0x91a80000 0x0 0x80000>; + no-map; + }; + + pil_camera_mem: pil-camera@95200000 { + reg = <0x0 0x95200000 0x0 0x700000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@95900000 { + reg = <0x0 0x95900000 0x0 0x1e00000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb@97700000 { + reg = <0x0 0x97700000 0x0 0x80000>; + no-map; + }; + + q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 { + reg = <0x0 0x97780000 0x0 0x80000>; + no-map; + }; + + pil_gdsp0_mem: pil-gdsp0@97800000 { + reg = <0x0 0x97800000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_mem: pil-gdsp1@99600000 { + reg = <0x0 0x99600000 0x0 0x1e00000>; + no-map; + }; + + q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 { + reg = <0x0 0x9b400000 0x0 0x80000>; + no-map; + }; + + q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 { + reg = <0x0 0x9b480000 0x0 0x80000>; + no-map; + }; + + pil_cdsp0_mem: pil-cdsp0@9b500000 { + reg = <0x0 0x9b500000 0x0 0x1e00000>; + no-map; + }; + + pil_gpu_mem: pil-gpu@9d300000 { + reg = <0x0 0x9d300000 0x0 0x2000>; + no-map; + }; + + q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 { + reg = <0x0 0x9d380000 0x0 0x80000>; + no-map; + }; + + pil_cdsp1_mem: pil-cdsp1@9d400000 { + reg = <0x0 0x9d400000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f200000 { + reg = <0x0 0x9f200000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9f900000 { + reg = <0x0 0x9f900000 0x0 0x1000000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1900000 { + reg = <0x0 0xd1900000 0x0 0x1c00000>; + no-map; + }; + }; + + firmware { + scm { + /delete-property/ memory-region; + }; + }; +};