| Message ID | 20250424062017.652969-2-uwu@icenowy.me |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: starfive: jh7110: support force inputs | expand |
On Tue, Apr 29, 2025 at 05:00:04PM GMT, Icenowy Zheng wrote: > > > > > +/* virtual pins for forcing GPI */ > > > > > +#define PAD_INTERNAL_LOW 254 > > > > > +#define PAD_INTERNAL_HIGH 255 > > > > > > > > Why this cannot be 20 and 21? These are not values for registers, > > > > but > > > > abstract numbers. > > > > > > The number must not collide with SYS GPIO pads too. > > > > There are no SYS GPIO pads here. Do you understand that this is not > > value for registers? > > Yes I understand. > > The situation is that JH7110 has two similar pin mux controllers, one > SYSGPIO and one AONGPIO. Despite I listed the values after the AONGPIO > pad list, these values should apply to SYSGPIO too (unless you want to > let them have different values for these two pinmux controllers), which > is the part with comment "sys_iomux pins". It is fine for me in such case. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h index 3865f01396395..3cca874b2bef7 100644 --- a/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h +++ b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h @@ -126,6 +126,10 @@ #define PAD_GMAC0_TXEN 18 #define PAD_GMAC0_TXC 19 +/* virtual pins for forcing GPI */ +#define PAD_INTERNAL_LOW 254 +#define PAD_INTERNAL_HIGH 255 + #define GPOUT_LOW 0 #define GPOUT_HIGH 1
The JH7110 SoC could support internal GPI signals to be routed to not external GPIO but internal low/high levels. Add two macros, PAD_INTERNAL_LOW and PAD_INTERNAL_HIGH, as two virtual "pads" to represent internal GPI sources with fixed low/high levels. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> --- include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h | 4 ++++ 1 file changed, 4 insertions(+)