diff mbox series

[2/6] accel/tcg: Don't use TARGET_LONG_BITS in decode_sleb128

Message ID 20250430230631.2571291-3-richard.henderson@linaro.org
State Superseded
Headers show
Series accel/tcg: Build translate-all, tcg-all twice | expand

Commit Message

Richard Henderson April 30, 2025, 11:06 p.m. UTC 
When we changed decode_sleb128 from target_long to
int64_t, we failed to adjust the shift limit.

Cc: qemu-stable@nongnu.org
Fixes: c9ad8d27caa ("tcg: Widen gen_insn_data to uint64_t")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/translate-all.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Pierrick Bouvier May 1, 2025, 6:31 a.m. UTC | #1 
On 4/30/25 4:06 PM, Richard Henderson wrote:
> When we changed decode_sleb128 from target_long to
> int64_t, we failed to adjust the shift limit.
> 
> Cc: qemu-stable@nongnu.org
> Fixes: c9ad8d27caa ("tcg: Widen gen_insn_data to uint64_t")
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   accel/tcg/translate-all.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Philippe Mathieu-Daudé May 1, 2025, 12:37 p.m. UTC | #2 
On 1/5/25 01:06, Richard Henderson wrote:
> When we changed decode_sleb128 from target_long to
> int64_t, we failed to adjust the shift limit.
> 
> Cc: qemu-stable@nongnu.org
> Fixes: c9ad8d27caa ("tcg: Widen gen_insn_data to uint64_t")
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   accel/tcg/translate-all.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff mbox series

Patch

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index fa4998b341..acf32e6c08 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -109,7 +109,7 @@  static int64_t decode_sleb128(const uint8_t **pp)
         val |= (int64_t)(byte & 0x7f) << shift;
         shift += 7;
     } while (byte & 0x80);
-    if (shift < TARGET_LONG_BITS && (byte & 0x40)) {
+    if (shift < 64 && (byte & 0x40)) {
         val |= -(int64_t)1 << shift;
     }