diff mbox series

phy: qcom: qmp-pcie: drop bogus x1e80100 qref supply

Message ID 20250429075440.19901-1-johan+linaro@kernel.org
State New
Headers show
Series phy: qcom: qmp-pcie: drop bogus x1e80100 qref supply | expand

Commit Message

Johan Hovold April 29, 2025, 7:54 a.m. UTC
The PCIe PHYs on x1e80100 do not a have a qref supply so stop requesting
one. This also avoids the follow warning at boot:

	qcom-qmp-pcie-phy 1be0000.phy: supply vdda-qref not found, using dummy regulator

Fixes: e961ec81a39b ("phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3")
Cc: Qiang Yu <quic_qianyu@quicinc.com>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Abel Vesa April 29, 2025, 8:01 a.m. UTC | #1
On 25-04-29 09:54:40, Johan Hovold wrote:
> The PCIe PHYs on x1e80100 do not a have a qref supply so stop requesting
> one. This also avoids the follow warning at boot:
> 
> 	qcom-qmp-pcie-phy 1be0000.phy: supply vdda-qref not found, using dummy regulator
> 
> Fixes: e961ec81a39b ("phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3")
> Cc: Qiang Yu <quic_qianyu@quicinc.com>
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Qiang Yu April 29, 2025, 8:24 a.m. UTC | #2
On 4/29/2025 3:54 PM, Johan Hovold wrote:
> The PCIe PHYs on x1e80100 do not a have a qref supply so stop requesting
> one. This also avoids the follow warning at boot:
>
> 	qcom-qmp-pcie-phy 1be0000.phy: supply vdda-qref not found, using dummy regulator
>
> Fixes: e961ec81a39b ("phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3")
> Cc: Qiang Yu <quic_qianyu@quicinc.com>
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---
We have QREF for each PCIe port on the X1E80100, all of which consume 
the regulator L3J. Although the PCIe PHY uses QREF indirectly, this 
creates a dependency, right? If PCIe doesn't vote for it, how can the 
PMIC driver decide when to disable L3J during system suspend or runtime 
suspend? Is there a chance that L3J could be disabled while PCIe still 
requires it?
>   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index c232b8fe9846..e5277ce9c136 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -4233,8 +4233,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = {
>   
>   	.reset_list		= sdm845_pciephy_reset_l,
>   	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),
> -	.vreg_list		= sm8550_qmp_phy_vreg_l,
> -	.num_vregs		= ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
> +	.vreg_list		= qmp_phy_vreg_l,
> +	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
>   	.regs			= pciephy_v6_regs_layout,
>   
>   	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
Johan Hovold April 29, 2025, 8:47 a.m. UTC | #3
On Tue, Apr 29, 2025 at 04:24:19PM +0800, Qiang Yu wrote:
> 
> On 4/29/2025 3:54 PM, Johan Hovold wrote:
> > The PCIe PHYs on x1e80100 do not a have a qref supply so stop requesting
> > one. This also avoids the follow warning at boot:
> >
> > 	qcom-qmp-pcie-phy 1be0000.phy: supply vdda-qref not found, using dummy regulator
> >
> > Fixes: e961ec81a39b ("phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3")
> > Cc: Qiang Yu <quic_qianyu@quicinc.com>
> > Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> > ---

> We have QREF for each PCIe port on the X1E80100, all of which consume 
> the regulator L3J. Although the PCIe PHY uses QREF indirectly, this 
> creates a dependency, right? 

The PHY binding should describe the direct dependencies for the PHY, so
the addition of qref for sm8550/sm8650 was probably also a mistake.
diff mbox series

Patch

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index c232b8fe9846..e5277ce9c136 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -4233,8 +4233,8 @@  static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = {
 
 	.reset_list		= sdm845_pciephy_reset_l,
 	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),
-	.vreg_list		= sm8550_qmp_phy_vreg_l,
-	.num_vregs		= ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
+	.vreg_list		= qmp_phy_vreg_l,
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
 	.regs			= pciephy_v6_regs_layout,
 
 	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,