Message ID | 20250418151235.27787-3-quic_ptalari@quicinc.com |
---|---|
State | Superseded |
Headers | show |
Series | Enable QUPs and Serial on SA8255p Qualcomm platforms | expand |
On Fri, Apr 18, 2025 at 08:42:28PM GMT, Praveen Talari wrote: > + interrupts: > + minItems: 1 > + items: > + - description: UART core irq > + - description: Wakeup irq (RX GPIO) > + > + interrupt-names: > + description: > + The UART interrupt and optionally the RX in-band wakeup interrupt. Drop description. It is not even accurate because you do not allow wakeup to be optional. > + items: > + - const: uart > + - const: wakeup > + > + power-domains: > + minItems: 2 > + maxItems: 2 > + > + power-domain-names: > + items: > + - const: power > + - const: perf > + > +required: > + - compatible > + - interrupts > + - reg Keep the same order as in properties. You already got comment about placement of 'reg'. Best regards, Krzysztof
Hi On 4/25/2025 3:42 PM, Krzysztof Kozlowski wrote: > On Fri, Apr 18, 2025 at 08:42:28PM GMT, Praveen Talari wrote: >> + interrupts: >> + minItems: 1 >> + items: >> + - description: UART core irq >> + - description: Wakeup irq (RX GPIO) >> + >> + interrupt-names: >> + description: >> + The UART interrupt and optionally the RX in-band wakeup interrupt. > Drop description. It is not even accurate because you do not allow > wakeup to be optional. Will update in next version. > >> + items: >> + - const: uart >> + - const: wakeup >> + >> + power-domains: >> + minItems: 2 >> + maxItems: 2 >> + >> + power-domain-names: >> + items: >> + - const: power >> + - const: perf >> + >> +required: >> + - compatible >> + - interrupts >> + - reg > Keep the same order as in properties. You already got comment about > placement of 'reg'. I agree, will update in next version > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml new file mode 100644 index 000000000000..85ee1ecef91e --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qcom,sa8255p-geni-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Geni based QUP UART interface + +maintainers: + - Praveen Talari <quic_ptalari@quicinc.com> + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + items: + - description: UART core irq + - description: Wakeup irq (RX GPIO) + + interrupt-names: + description: + The UART interrupt and optionally the RX in-band wakeup interrupt. + items: + - const: uart + - const: wakeup + + power-domains: + minItems: 2 + maxItems: 2 + + power-domain-names: + items: + - const: power + - const: perf + +required: + - compatible + - interrupts + - reg + - power-domains + - power-domain-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + serial@990000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x990000 0x4000>; + interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>; + power-domain-names = "power", "perf"; + }; +...