[RFC,0/3] pinctrl: starfive: jh7110: support force inputs

The input signals inside the JH7110 SoC (to be routed by the pin
controller) could be routed to GPIOs and internal fixed low/high levels.
As the total GPIO count of JH7110 is not very high, it's sometime
feasible to omit some hardwiring outside the SoC and do them in the pin
controller. One such example is the USB overcurrent_n signal, which
defaults to low at SoC reset, needs to be high for the USB controller to
correctly work (the _n means low indicates overcurrent situation) and
gets omitted on the Pine64 Star64 board.

Add the support for hardwiring GPI signals inside the JH7110 pin
controllers, via two new DT properties. The patchset is tagged RFC
because I personally feel the DT binding a little dirty and not
scalable, but the currently specially-encoded pinmux property makes me
feeling dirty too, and especially dirty if adding virtual pins to mean
internal low/high (and these virtual pins should be sharable among
multiple signals, which seems to be not so desirable for pinconfs).

Icenowy Zheng (3):
  dt-bindings: pinctrl: jh7110-sys: add force inputs
  pinctrl: starfive: jh7110: support forcing inputs to low/high
  riscv: dts: starfive: jh7110-pine64-star64: force no USB overcurrent

 .../pinctrl/starfive,jh7110-sys-pinctrl.yaml  | 10 +++++
 .../dts/starfive/jh7110-pine64-star64.dts     |  2 +
 .../starfive/pinctrl-starfive-jh7110.c        | 43 +++++++++++++++++++
 3 files changed, 55 insertions(+)

Hi Icenowy,

thanks for your patch!

On Tue, Apr 22, 2025 at 6:23 PM Icenowy Zheng <uwu@icenowy.me> wrote:

> +  starfive,force-low-inputs:
> +    description:
> +      The list of input signals forced to be low inside the SoC itself.
> +    $ref: /schemas/types.yaml#/definitions/uint32-array

I don't see why you need this hack.

Use the existing per-pin output-low property (see
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml).

> +  starfive,force-high-inputs:
> +    description:
> +      The list of input signals forced to be high inside the SoC itself.
> +    $ref: /schemas/types.yaml#/definitions/uint32-array

Use the existing output-high property.

Now I *know* these two properties are per-pin. That is more talkative
but way easier for users to read.

Then use pincontrol hogs to make sure these configs are set up
at probe.

Yours,
Linus Walleij

于 2025年4月23日 GMT+08:00 17:09:42，Linus Walleij <linus.walleij@linaro.org> 写道：
>Hi Icenowy,
>
>thanks for your patch!
>
>On Tue, Apr 22, 2025 at 6:23 PM Icenowy Zheng <uwu@icenowy.me> wrote:
>
>> +  starfive,force-low-inputs:
>> +    description:
>> +      The list of input signals forced to be low inside the SoC itself.
>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>
>I don't see why you need this hack.

Unfortunately these properties are not for pins, but internal signals that isn't
bound to external pins.

>
>Use the existing per-pin output-low property (see
>Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml).
>
>> +  starfive,force-high-inputs:
>> +    description:
>> +      The list of input signals forced to be high inside the SoC itself.
>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>
>Use the existing output-high property.
>
>Now I *know* these two properties are per-pin. That is more talkative
>but way easier for users to read.
>
>Then use pincontrol hogs to make sure these configs are set up
>at probe.
>
>Yours,
>Linus Walleij

On Wed, Apr 23, 2025 at 11:41 AM Icenowy Zheng <uwu@icenowy.me> wrote:
> 于 2025年4月23日 GMT+08:00 17:09:42，Linus Walleij <linus.walleij@linaro.org> 写道：
> >Hi Icenowy,
> >
> >thanks for your patch!
> >
> >On Tue, Apr 22, 2025 at 6:23 PM Icenowy Zheng <uwu@icenowy.me> wrote:
> >
> >> +  starfive,force-low-inputs:
> >> +    description:
> >> +      The list of input signals forced to be low inside the SoC itself.
> >> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> >
> >I don't see why you need this hack.
>
> Unfortunately these properties are not for pins, but internal signals that isn't
> bound to external pins.

We don't really care if pins are external or not, we are an operating system
not a philosophy department ;)

You calculate the offset and shift like this and write into a base+offset:

+                       offset = 4 * (pin / 4);
+                       shift  = 8 * (pin % 4);
+
+                       val = readl_relaxed(sfp->base +
+                                           info->gpi_reg_base + offset);

Compare to jh7110_pin_dbg_show():

               unsigned int offset = 4 * (pin / 4);
                unsigned int shift  = 8 * (pin % 4);
                u32 dout = readl_relaxed(sfp->base +
info->dout_reg_base + offset);
                u32 doen = readl_relaxed(sfp->base +
info->doen_reg_base + offset);

So clearly the entities that you affect are in the same numberspace,
and that is all we care about. They are not enumerated in any way
orthogonal to any other pins AFAICT.

Both pin control and GPIO handle chip-internal lines that are not
routed outside sometimes, that's fine. Just deal with them as any other
"pins".

Yours,
Linus Walleij

On Wed, Apr 23, 2025 at 4:22 PM Icenowy Zheng <uwu@icenowy.me> wrote:

> > So clearly the entities that you affect are in the same numberspace,
> > and that is all we care about. They are not enumerated in any way
> > orthogonal to any other pins AFAICT.
>
> They just share the field width, they're not in the same numberspace.

OK I trust you on this, I just had to put a bit of pressure so we try
to stay with standard bindings.

> The design of the JH7110 pin mux control is quite simple and stupid:
>
> - First per-GPIO map configuration to map the GPIO's DOEn pin to
> internal tri-stating signals.
> - Then per-GPIO map configuration to map the GPIO's DOUT pin to
> internal output signals.
> - Then per-input-signal configuration (note that it's no longer per-
> GPIO) map configuration to map the signal to a GPIO's DIN (or fixed
> low/high).

I get it, I think.

So if I understand correctly this set-up is necessary to use any one
pin as a GPIO pin?

In that case, consider that this must probably be deeply integrated
with the GPIO subsystem rather than the pin control subsystem.

For example GPIO usually has this:

gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;

Indicating which pins are actually routed as GPIO and implicitly
contains the information you need as to which pins are
affected.

There is also

gpio-reserved-ranges = <0 4>, <12 2>;

that can be used to say certain number ranges in the GPIO
controller can *not* be used for GPIO.

This type of inferred information should ideally be used to
infer the configuration rather than hardcoded properties.

And if you have pin control as a back-end to GPIO, the
callbacks in struct pinmux_ops:

        int (*gpio_request_enable) (struct pinctrl_dev *pctldev,
                                    struct pinctrl_gpio_range *range,
                                    unsigned int offset);
        void (*gpio_disable_free) (struct pinctrl_dev *pctldev,
                                   struct pinctrl_gpio_range *range,
                                   unsigned int offset);
        int (*gpio_set_direction) (struct pinctrl_dev *pctldev,
                                   struct pinctrl_gpio_range *range,
                                   unsigned int offset,
                                   bool input);

which you could implement in jh7110_pinmux_ops to get
a tighter connection between you pinmux and GPIO controller
portions.

I have a strong feeling that the missing piece is using these
callbacks along with the gpio-ranges to connect the GPIO and
pin mux systems together so that you can set this stuff up
in the above callbacks instead.

That would save you the weird DT properties that will be a real
pain to keep in sync with the actual use.

Yours,
Linus Walleij