| Message ID | 20250210155605.575367-3-quic_vikramsa@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: sa8775p: Add sa8775p camss support | expand |
On 2/10/25 4:56 PM, Vikram Sharma wrote: > Add changes to support the camera subsystem on the SA8775P. > > Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 187 ++++++++++++++++++++++++++ > 1 file changed, 187 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 3394ae2d1300..83640fef05d2 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -7,6 +7,7 @@ > #include <dt-bindings/interconnect/qcom,icc.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/qcom,rpmh.h> > +#include <dt-bindings/clock/qcom,sa8775p-camcc.h> > #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> > #include <dt-bindings/clock/qcom,sa8775p-gcc.h> > #include <dt-bindings/clock/qcom,sa8775p-gpucc.h> > @@ -3796,6 +3797,192 @@ videocc: clock-controller@abf0000 { > #power-domain-cells = <1>; > }; > > + camss: isp@ac7a000 { > + compatible = "qcom,sa8775p-camss"; > + > + reg = <0x0 0xac7a000 0x0 0x0f01>, > + <0x0 0xac7c000 0x0 0x0f01>, > + <0x0 0xac84000 0x0 0x0f01>, > + <0x0 0xac88000 0x0 0x0f01>, > + <0x0 0xac8c000 0x0 0x0f01>, > + <0x0 0xac90000 0x0 0x0f01>, > + <0x0 0xac94000 0x0 0x0f01>, These I think should begin 0x1000 earlier and as a result be 0x1000 longer I also believe this is an off-by-one.. there's nothing past a certain register in there, but 0xf00 is what I believe makes more sense here [...] > + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, > + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&gcc GCC_CAMERA_SF_AXI_CLK>, Please don't forcefully align these [...] > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; The last one should probably be always-on, given we're doing all voting on the APPS RSC as of right now otherwise looks reasonable Konrad
On 2/10/25 4:56 PM, Vikram Sharma wrote: > Add changes to support the camera subsystem on the SA8775P. > > Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > --- [...] > + interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 760> + <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 759 > + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 762 > + <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 761 Konrad
On 4/16/25 5:29 PM, Vikram Sharma wrote: > > On 4/14/2025 7:14 PM, Konrad Dybcio wrote: >> On 2/10/25 4:56 PM, Vikram Sharma wrote: >>> Add changes to support the camera subsystem on the SA8775P. >>> >>> Co-developed-by: Suresh Vankadara<quic_svankada@quicinc.com> >>> Signed-off-by: Suresh Vankadara<quic_svankada@quicinc.com> >>> Signed-off-by: Vikram Sharma<quic_vikramsa@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 187 ++++++++++++++++++++++++++ >>> 1 file changed, 187 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> index 3394ae2d1300..83640fef05d2 100644 >>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> @@ -7,6 +7,7 @@ >>> #include <dt-bindings/interconnect/qcom,icc.h> >>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>> #include <dt-bindings/clock/qcom,rpmh.h> >>> +#include <dt-bindings/clock/qcom,sa8775p-camcc.h> >>> #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> >>> #include <dt-bindings/clock/qcom,sa8775p-gcc.h> >>> #include <dt-bindings/clock/qcom,sa8775p-gpucc.h> >>> @@ -3796,6 +3797,192 @@ videocc: clock-controller@abf0000 { >>> #power-domain-cells = <1>; >>> }; >>> + camss: isp@ac7a000 { >>> + compatible = "qcom,sa8775p-camss"; >>> + >>> + reg = <0x0 0xac7a000 0x0 0x0f01>, >>> + <0x0 0xac7c000 0x0 0x0f01>, >>> + <0x0 0xac84000 0x0 0x0f01>, >>> + <0x0 0xac88000 0x0 0x0f01>, >>> + <0x0 0xac8c000 0x0 0x0f01>, >>> + <0x0 0xac90000 0x0 0x0f01>, >>> + <0x0 0xac94000 0x0 0x0f01>, >> These I think should begin 0x1000 earlier and as a result be 0x1000 > Hi Konrad, > Thanks for your comments. > First 0x1000 bytes of CSID are for secure usecase. Actually CSID register address space starts from > 'TITAN_A_RT_1_CSID_WRAPPER_CLC_CSID0_HW_VERSION' which is 0xac7a000. Alright, thanks Konrad
On 4/14/2025 7:18 PM, Konrad Dybcio wrote: > On 2/10/25 4:56 PM, Vikram Sharma wrote: >> Add changes to support the camera subsystem on the SA8775P. >> >> Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com> >> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> >> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> >> --- > [...] > >> + interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, > 760> + <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, Hi Konrad, We cross checked internal documents to confirm IRQ number for csid_lite2/3 and vfe_lite2/3 Calculation for IRQ number is done with respect to vector number as irq_num = (vector - 32). csid_lite2 vector -> 791 csid_lite3 vector -> 790 vfe_lite2 vector -> 793 vfe_lite3 vector -> 792 thus irqs are as csid_lite2 -> 759 csid_lite3 -> 758 vfe_lite2 -> 761 vfe_lite3 -> 760 Please let me know if this looks fine to you? > > 759 > >> + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, > 762 > >> + <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, > 761 > > Konrad Best Regards, Vikram
On 4/18/25 9:28 AM, Vikram Sharma wrote: > > On 4/14/2025 7:18 PM, Konrad Dybcio wrote: >> On 2/10/25 4:56 PM, Vikram Sharma wrote: >>> Add changes to support the camera subsystem on the SA8775P. >>> >>> Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com> >>> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> >>> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> >>> --- >> [...] >> >>> + interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, >>> + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, >>> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, >>> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, >>> + <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, >> 760> + <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, > > Hi Konrad, > > We cross checked internal documents to confirm IRQ number for csid_lite2/3 and vfe_lite2/3 > Calculation for IRQ number is done with respect to vector number as > irq_num = (vector - 32). > csid_lite2 vector -> 791 > csid_lite3 vector -> 790 > vfe_lite2 vector -> 793 > vfe_lite3 vector -> 792 > > thus irqs are as > csid_lite2 -> 759 > csid_lite3 -> 758 > vfe_lite2 -> 761 > vfe_lite3 -> 760 > > Please let me know if this looks fine to you? We had a similar issue with qcs8300 - the reported vector id skipped a number at some point. In that case the SPI ports indices alongside them were advised to be used. Please check with the HW team, but I suppose this would be the case for this one too. Konrad
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 3394ae2d1300..83640fef05d2 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sa8775p-camcc.h> #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> #include <dt-bindings/clock/qcom,sa8775p-gcc.h> #include <dt-bindings/clock/qcom,sa8775p-gpucc.h> @@ -3796,6 +3797,192 @@ videocc: clock-controller@abf0000 { #power-domain-cells = <1>; }; + camss: isp@ac7a000 { + compatible = "qcom,sa8775p-camss"; + + reg = <0x0 0xac7a000 0x0 0x0f01>, + <0x0 0xac7c000 0x0 0x0f01>, + <0x0 0xac84000 0x0 0x0f01>, + <0x0 0xac88000 0x0 0x0f01>, + <0x0 0xac8c000 0x0 0x0f01>, + <0x0 0xac90000 0x0 0x0f01>, + <0x0 0xac94000 0x0 0x0f01>, + <0x0 0xac78000 0x0 0x1000>, + <0x0 0xac9c000 0x0 0x2000>, + <0x0 0xac9e000 0x0 0x2000>, + <0x0 0xaca0000 0x0 0x2000>, + <0x0 0xaca2000 0x0 0x2000>, + <0x0 0xacac000 0x0 0x0400>, + <0x0 0xacad000 0x0 0x0400>, + <0x0 0xacae000 0x0 0x0400>, + <0x0 0xac4d000 0x0 0xd000>, + <0x0 0xac5a000 0x0 0xd000>, + <0x0 0xac85000 0x0 0x0d00>, + <0x0 0xac89000 0x0 0x0d00>, + <0x0 0xac8d000 0x0 0x0d00>, + <0x0 0xac91000 0x0 0x0d00>, + <0x0 0xac95000 0x0 0x0d00>; + reg-names = "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_ife_lite", + "cpas_vfe0", + "cpas_vfe1", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "icp_ahb", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csid-lite0", + "csid-lite1", + "csid-lite2", + "csid-lite3", + "csid-lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe-lite0", + "vfe-lite1", + "vfe-lite2", + "vfe-lite3", + "vfe-lite4"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ahb", + "hf_0", + "sf_0"; + + iommus = <&apps_smmu 0x3400 0x20>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,sa8775p-camcc"; reg = <0x0 0x0ade0000 0x0 0x20000>;