| Message ID | 20230110164406.94366-7-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/arm: Move various objects to softmmu_ss to build them once (part 1) | expand |
Cc'ing Pierrick On 10/1/23 17:43, Philippe Mathieu-Daudé wrote: > Units including "target/arm/cpu.h" can't be built once via meson's > softmmu_ss[] source set. Since this header depends on specific > definitions such the word size (32 or 64-bit), for ARM such units > must go to the per-target arm_ss[]. > > We want to expose few architectural definitions to hardware models. > > Expose the ARM architectural definitions used by hardware models, > in order to reduce the inclusion of "target/arm/cpu.h". > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > include/hw/arm/cpu.h | 49 ++++++++++++++++++++++++++++++++++++++++++++ Richard, WRT your comment in previous patch (target/ shouldn't access hw/), WDYT of "target/arm/hw-defs.h" for this header? > target/arm/cpu-qom.h | 15 -------------- > target/arm/cpu.h | 34 ------------------------------ > 3 files changed, 49 insertions(+), 49 deletions(-) > > diff --git a/include/hw/arm/cpu.h b/include/hw/arm/cpu.h > index 0c5d6ca2a8..6758bffe34 100644 > --- a/include/hw/arm/cpu.h > +++ b/include/hw/arm/cpu.h > @@ -25,4 +25,53 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) > #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU > #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) > > +enum QemuPsciConduit { > + QEMU_PSCI_CONDUIT_DISABLED = 0, > + QEMU_PSCI_CONDUIT_SMC = 1, > + QEMU_PSCI_CONDUIT_HVC = 2, > +}; > + > +/* Meanings of the ARMCPU object's four inbound GPIO lines */ > +#define ARM_CPU_IRQ 0 > +#define ARM_CPU_FIQ 1 > +#define ARM_CPU_VIRQ 2 > +#define ARM_CPU_VFIQ 3 > + > +#define GTIMER_PHYS 0 > +#define GTIMER_VIRT 1 > +#define GTIMER_HYP 2 > +#define GTIMER_SEC 3 > +#define GTIMER_HYPVIRT 4 > +#define NUM_GTIMERS 5 > + > +/* For M profile, some registers are banked secure vs non-secure; > + * these are represented as a 2-element array where the first element > + * is the non-secure copy and the second is the secure copy. > + * When the CPU does not have implement the security extension then > + * only the first element is used. > + * This means that the copy for the current security state can be > + * accessed via env->registerfield[env->v7m.secure] (whether the security > + * extension is implemented or not). > + */ > +enum { > + M_REG_NS = 0, > + M_REG_S = 1, > + M_REG_NUM_BANKS = 2, > +}; > + > +#define ARM_AFF0_SHIFT 0 > +#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) > +#define ARM_AFF1_SHIFT 8 > +#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) > +#define ARM_AFF2_SHIFT 16 > +#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) > +#define ARM_AFF3_SHIFT 32 > +#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) > +#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 > + > +#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) > +#define ARM64_AFFINITY_MASK \ > + (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) > +#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) > + > #endif > diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h > index b98904b6bc..d37037e214 100644 > --- a/target/arm/cpu-qom.h > +++ b/target/arm/cpu-qom.h > @@ -68,19 +68,4 @@ void arm_gt_htimer_cb(void *opaque); > void arm_gt_stimer_cb(void *opaque); > void arm_gt_hvtimer_cb(void *opaque); > > -#define ARM_AFF0_SHIFT 0 > -#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) > -#define ARM_AFF1_SHIFT 8 > -#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) > -#define ARM_AFF2_SHIFT 16 > -#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) > -#define ARM_AFF3_SHIFT 32 > -#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) > -#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 > - > -#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) > -#define ARM64_AFFINITY_MASK \ > - (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) > -#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) > - > #endif > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 52ac99cad3..ab6fdecf48 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -72,21 +72,6 @@ > #define ARMV7M_EXCP_PENDSV 14 > #define ARMV7M_EXCP_SYSTICK 15 > > -/* For M profile, some registers are banked secure vs non-secure; > - * these are represented as a 2-element array where the first element > - * is the non-secure copy and the second is the secure copy. > - * When the CPU does not have implement the security extension then > - * only the first element is used. > - * This means that the copy for the current security state can be > - * accessed via env->registerfield[env->v7m.secure] (whether the security > - * extension is implemented or not). > - */ > -enum { > - M_REG_NS = 0, > - M_REG_S = 1, > - M_REG_NUM_BANKS = 2, > -}; > - > /* ARM-specific interrupt pending bits. */ > #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 > #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 > @@ -107,12 +92,6 @@ enum { > #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) > #endif > > -/* Meanings of the ARMCPU object's four inbound GPIO lines */ > -#define ARM_CPU_IRQ 0 > -#define ARM_CPU_FIQ 1 > -#define ARM_CPU_VIRQ 2 > -#define ARM_CPU_VFIQ 3 > - > /* ARM-specific extra insn start words: > * 1: Conditional execution bits > * 2: Partial exception syndrome for data aborts > @@ -160,13 +139,6 @@ typedef struct ARMGenericTimer { > uint64_t ctl; /* Timer Control register */ > } ARMGenericTimer; > > -#define GTIMER_PHYS 0 > -#define GTIMER_VIRT 1 > -#define GTIMER_HYP 2 > -#define GTIMER_SEC 3 > -#define GTIMER_HYPVIRT 4 > -#define NUM_GTIMERS 5 > - > #define VTCR_NSW (1u << 29) > #define VTCR_NSA (1u << 30) > #define VSTCR_SW VTCR_NSW > @@ -3323,12 +3295,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env) > void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, > target_ulong *cs_base, uint32_t *flags); > > -enum { > - QEMU_PSCI_CONDUIT_DISABLED = 0, > - QEMU_PSCI_CONDUIT_SMC = 1, > - QEMU_PSCI_CONDUIT_HVC = 2, > -}; > - > #ifndef CONFIG_USER_ONLY > /* Return the address space index to use for a memory access */ > static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
diff --git a/include/hw/arm/cpu.h b/include/hw/arm/cpu.h index 0c5d6ca2a8..6758bffe34 100644 --- a/include/hw/arm/cpu.h +++ b/include/hw/arm/cpu.h @@ -25,4 +25,53 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) +enum QemuPsciConduit { + QEMU_PSCI_CONDUIT_DISABLED = 0, + QEMU_PSCI_CONDUIT_SMC = 1, + QEMU_PSCI_CONDUIT_HVC = 2, +}; + +/* Meanings of the ARMCPU object's four inbound GPIO lines */ +#define ARM_CPU_IRQ 0 +#define ARM_CPU_FIQ 1 +#define ARM_CPU_VIRQ 2 +#define ARM_CPU_VFIQ 3 + +#define GTIMER_PHYS 0 +#define GTIMER_VIRT 1 +#define GTIMER_HYP 2 +#define GTIMER_SEC 3 +#define GTIMER_HYPVIRT 4 +#define NUM_GTIMERS 5 + +/* For M profile, some registers are banked secure vs non-secure; + * these are represented as a 2-element array where the first element + * is the non-secure copy and the second is the secure copy. + * When the CPU does not have implement the security extension then + * only the first element is used. + * This means that the copy for the current security state can be + * accessed via env->registerfield[env->v7m.secure] (whether the security + * extension is implemented or not). + */ +enum { + M_REG_NS = 0, + M_REG_S = 1, + M_REG_NUM_BANKS = 2, +}; + +#define ARM_AFF0_SHIFT 0 +#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) +#define ARM_AFF1_SHIFT 8 +#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) +#define ARM_AFF2_SHIFT 16 +#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) +#define ARM_AFF3_SHIFT 32 +#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) +#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 + +#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) +#define ARM64_AFFINITY_MASK \ + (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) +#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) + #endif diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index b98904b6bc..d37037e214 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -68,19 +68,4 @@ void arm_gt_htimer_cb(void *opaque); void arm_gt_stimer_cb(void *opaque); void arm_gt_hvtimer_cb(void *opaque); -#define ARM_AFF0_SHIFT 0 -#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) -#define ARM_AFF1_SHIFT 8 -#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) -#define ARM_AFF2_SHIFT 16 -#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) -#define ARM_AFF3_SHIFT 32 -#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) -#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 - -#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) -#define ARM64_AFFINITY_MASK \ - (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) -#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) - #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 52ac99cad3..ab6fdecf48 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -72,21 +72,6 @@ #define ARMV7M_EXCP_PENDSV 14 #define ARMV7M_EXCP_SYSTICK 15 -/* For M profile, some registers are banked secure vs non-secure; - * these are represented as a 2-element array where the first element - * is the non-secure copy and the second is the secure copy. - * When the CPU does not have implement the security extension then - * only the first element is used. - * This means that the copy for the current security state can be - * accessed via env->registerfield[env->v7m.secure] (whether the security - * extension is implemented or not). - */ -enum { - M_REG_NS = 0, - M_REG_S = 1, - M_REG_NUM_BANKS = 2, -}; - /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 @@ -107,12 +92,6 @@ enum { #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #endif -/* Meanings of the ARMCPU object's four inbound GPIO lines */ -#define ARM_CPU_IRQ 0 -#define ARM_CPU_FIQ 1 -#define ARM_CPU_VIRQ 2 -#define ARM_CPU_VFIQ 3 - /* ARM-specific extra insn start words: * 1: Conditional execution bits * 2: Partial exception syndrome for data aborts @@ -160,13 +139,6 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; -#define GTIMER_PHYS 0 -#define GTIMER_VIRT 1 -#define GTIMER_HYP 2 -#define GTIMER_SEC 3 -#define GTIMER_HYPVIRT 4 -#define NUM_GTIMERS 5 - #define VTCR_NSW (1u << 29) #define VTCR_NSA (1u << 30) #define VSTCR_SW VTCR_NSW @@ -3323,12 +3295,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags); -enum { - QEMU_PSCI_CONDUIT_DISABLED = 0, - QEMU_PSCI_CONDUIT_SMC = 1, - QEMU_PSCI_CONDUIT_HVC = 2, -}; - #ifndef CONFIG_USER_ONLY /* Return the address space index to use for a memory access */ static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
Units including "target/arm/cpu.h" can't be built once via meson's softmmu_ss[] source set. Since this header depends on specific definitions such the word size (32 or 64-bit), for ARM such units must go to the per-target arm_ss[]. We want to expose few architectural definitions to hardware models. Expose the ARM architectural definitions used by hardware models, in order to reduce the inclusion of "target/arm/cpu.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- include/hw/arm/cpu.h | 49 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu-qom.h | 15 -------------- target/arm/cpu.h | 34 ------------------------------ 3 files changed, 49 insertions(+), 49 deletions(-)