| Message ID | 20250221-sar2130p-pci-v3-0-61a0fdfb75b4@linaro.org |
|---|---|
| Headers | show |
| Series | PCI: qcom-ep: add support for using the EP on SAR2130P and SM8450 | expand |
On Fri, Feb 21, 2025 at 05:51:59PM +0200, Dmitry Baryshkov wrote: > Qualcomm SA8775P supports cache coherency on the PCIe EP controller. > Allow 'dma-coherent' property to be used for this device. This fixes > a part of the following error (the second part is fixed in the next > commit): > > pcie-ep@1c10000: Unevaluated properties are not allowed ('dma-coherent', 'iommus' were unexpected) > > Fixes: 4b220c6fa9f3 ("arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Fri, Feb 21, 2025 at 05:52:01PM +0200, Dmitry Baryshkov wrote: > Qualcomm SM8450 platform can (and should) be using DMA for the PCIe EP > transfers. Extend the MMIO regions and interrupts in order to acommodate > for the DMA resources, mark iommus property as required for the > platform. > > Upstream DT doesn't provide support for the EP mode of the PCIe > controller, so while this is an ABI break, it doesn't break any of the > supported platforms. > > Fixes: 63e445b746aa ("dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC") > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Fri, Feb 21, 2025 at 05:51:59PM +0200, Dmitry Baryshkov wrote: > Qualcomm SA8775P supports cache coherency on the PCIe EP controller. > Allow 'dma-coherent' property to be used for this device. This fixes > a part of the following error (the second part is fixed in the next > commit): > > pcie-ep@1c10000: Unevaluated properties are not allowed ('dma-coherent', 'iommus' were unexpected) > > Fixes: 4b220c6fa9f3 ("arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > index 1226ee5d08d1ae909b07b0d78014618c4c74e9a8..0c2ca4cfa3b190b3fb204f0d7142370734fb3534 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > @@ -91,6 +91,8 @@ properties: > - const: pcie-mem > - const: cpu-pcie > > + dma-coherent: true > + > resets: > maxItems: 1 > > > -- > 2.39.5 >
On Fri, Feb 21, 2025 at 05:52:02PM +0200, Dmitry Baryshkov wrote: > On Qualcomm platforms here are two major kinds of PCIe EP controllers: > ones which use eDMA and IOMMU and the ones which do not (like SDX55 / > SDX65). It doesn't make sense to c&p similar properties all over the > place. Merge these two usecases into a single conditional clause. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 68 +++++++++++----------- > 1 file changed, 35 insertions(+), 33 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > index d22022ff2760c5aa84d31e3c719dd4b63adbb4cf..2c1918ca30dcfa8decea684ff6bfe11c602bbc7e 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > @@ -131,6 +131,7 @@ required: > > allOf: > - $ref: pci-ep.yaml# > + > - if: > properties: > compatible: > @@ -140,9 +141,43 @@ allOf: > then: > properties: > reg: > + minItems: 6 > maxItems: 6 > reg-names: > + minItems: 6 > maxItems: 6 > + interrupts: > + minItems: 2 > + maxItems: 2 > + interrupt-names: > + minItems: 2 > + maxItems: 2 > + iommus: false > + else: > + properties: > + reg: > + minItems: 7 > + maxItems: 7 > + reg-names: > + minItems: 7 > + maxItems: 7 > + interrupts: > + minItems: 3 > + maxItems: 3 > + interrupt-names: > + minItems: 3 > + maxItems: 3 > + required: > + - iommus > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,sdx55-pcie-ep > + then: > + properties: > clocks: > items: > - description: PCIe Auxiliary clock > @@ -161,11 +196,6 @@ allOf: > - const: slave_q2a > - const: sleep > - const: ref > - interrupts: > - maxItems: 2 > - interrupt-names: > - maxItems: 2 > - iommus: false > > - if: > properties: > @@ -175,12 +205,6 @@ allOf: > - qcom,sm8450-pcie-ep > then: > properties: > - reg: > - minItems: 7 > - maxItems: 7 > - reg-names: > - minItems: 7 > - maxItems: 7 > clocks: > items: > - description: PCIe Auxiliary clock > @@ -201,14 +225,6 @@ allOf: > - const: ref > - const: ddrss_sf_tbu > - const: aggre_noc_axi > - interrupts: > - minItems: 3 > - maxItems: 3 > - interrupt-names: > - minItems: 3 > - maxItems: 3 > - required: > - - iommus > > - if: > properties: > @@ -218,12 +234,6 @@ allOf: > - qcom,sa8775p-pcie-ep > then: > properties: > - reg: > - minItems: 7 > - maxItems: 7 > - reg-names: > - minItems: 7 > - maxItems: 7 > clocks: > items: > - description: PCIe Auxiliary clock > @@ -238,14 +248,6 @@ allOf: > - const: bus_master > - const: bus_slave > - const: slave_q2a > - interrupts: > - minItems: 3 > - maxItems: 3 > - interrupt-names: > - minItems: 3 > - maxItems: 3 > - required: > - - iommus > > unevaluatedProperties: false > > > -- > 2.39.5 >
Update the incomplete SM8450 support and bring in SAR2130P support for the PCIe1 controller to be used in EP mode. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- Changes in v3: - Rephrased commit messages, adding notes regarding ABI breaks (Krzysztof) - Added missing minTems (Krzysztof) - Reworked schema, merging reg/-names and interrupts/-names to a single conditional clause. - Added dma-coherent to the list of allowed properties. - Link to v2: https://lore.kernel.org/r/20250221-sar2130p-pci-v2-0-cc87590ffbeb@linaro.org Changes in v2: - Rephrase IOMMU commit message to stop mentioning eDMA (Mani) - Explain why it is impossible to use fallback compatibles (Mani) - Reformat names to vertical lists (Konrad) - Use ACTIVE_ONLY for cpu-pcie interconnect (Konrad) - Use tags for sm8450 interconnects (Konrad) - Link to v1: https://lore.kernel.org/r/20250217-sar2130p-pci-v1-0-94b20ec70a14@linaro.org --- Dmitry Baryshkov (8): dt-bindings: PCI: qcom-ep: describe optional dma-coherent property dt-bindings: PCI: qcom-ep: describe optional IOMMU dt-bindings: PCI: qcom-ep: enable DMA for SM8450 dt-bindings: PCI: qcom-ep: consolidate DMA vs non-DMA usecases dt-bindings: PCI: qcom-ep: add SAR2130P compatible PCI: dwc: pcie-qcom-ep: enable EP support for SAR2130P arm64: dts: qcom: sar2130p: add PCIe EP device nodes arm64: dts: qcom: sm8450: add PCIe EP device nodes .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 100 +++++++++++++++------ arch/arm64/boot/dts/qcom/sar2130p.dtsi | 61 +++++++++++++ arch/arm64/boot/dts/qcom/sm8450.dtsi | 62 +++++++++++++ drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 4 files changed, 198 insertions(+), 26 deletions(-) --- base-commit: 6b063ae40049a93bc662cb0c1653a691424b11a1 change-id: 20241017-sar2130p-pci-80dae35a67e8 Best regards,