| Message ID | 20250113-sm8750_usb_master-v1-0-09afe1dc2524@quicinc.com |
|---|---|
| Headers | show |
| Series | phy: qcom: Introduce USB support for SM8750 | expand |
On Mon, 13 Jan 2025 13:52:08 -0800, Melody Olvera wrote: > From: Wesley Cheng <quic_wcheng@quicinc.com> > > On SM8750, the M31 eUSB2 PHY is being used to support USB2. Add the > binding definition for the PHY driver. > > Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com> > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > .../bindings/phy/qcom,m31-eusb2-phy.yaml | 84 ++++++++++++++++++++++ > 1 file changed, 84 insertions(+) > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.example.dts:18:18: fatal error: dt-bindings/clock/qcom,sm8750-gcc.h: No such file or directory 18 | #include <dt-bindings/clock/qcom,sm8750-gcc.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[2]: *** [scripts/Makefile.dtbs:131: Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.example.dtb] Error 1 make[2]: *** Waiting for unfinished jobs.... make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1506: dt_binding_check] Error 2 make: *** [Makefile:251: __sub-make] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250113-sm8750_usb_master-v1-2-09afe1dc2524@quicinc.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On Mon, Jan 13, 2025 at 01:52:12PM -0800, Melody Olvera wrote:
> Add configs for the M31 eUSB2 PHY for SM8750 USB.
What is SM8750? Which company? Which board needs it? That's a defconfig
for all platforms, not only for your SoC.
Best regards,
Krzysztof
Hi, On 13/01/2025 22:52, Melody Olvera wrote: > From: Wesley Cheng <quic_wcheng@quicinc.com> > > On SM8750, the eUSB2 PHY used is M31 based. Add the initialization > sequences to bring it out of reset, and to initialize the associated eUSB2 > repeater as well. > > Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com> > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > drivers/phy/qualcomm/Kconfig | 12 +- > drivers/phy/qualcomm/Makefile | 1 + > drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 269 ++++++++++++++++++++++++++++++ > 3 files changed, 281 insertions(+), 1 deletion(-) > > diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig > index 846f8c99547fd5132feaa1e41093b8eab51714f9..8c265ae86c7b9ddcb66b42626557ea130b674001 100644 > --- a/drivers/phy/qualcomm/Kconfig > +++ b/drivers/phy/qualcomm/Kconfig > @@ -140,7 +140,7 @@ config PHY_QCOM_EUSB2_REPEATER > select GENERIC_PHY > help > Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm > - PMICs. The repeater is paired with a Synopsys eUSB2 Phy > + PMICs. The repeater can be paired with a Synopsys or M31 eUSB2 Phy This should be a separate patch > on Qualcomm SOCs. > > config PHY_QCOM_M31_USB > @@ -154,6 +154,16 @@ config PHY_QCOM_M31_USB > management. This driver is required even for peripheral only or > host only mode configurations. > > +config PHY_QCOM_M31_EUSB > + tristate "Qualcomm M31 eUSB2 PHY driver support" > + depends on USB && (ARCH_QCOM || COMPILE_TEST) > + select GENERIC_PHY > + help > + Enable this to support M31 EUSB2 PHY transceivers on Qualcomm > + chips with DWC3 USB core. It supports initializing and cleaning > + up of the associated USB repeater that is paired with the eUSB2 > + PHY. > + > config PHY_QCOM_USB_HS > tristate "Qualcomm USB HS PHY module" > depends on USB_ULPI_BUS > diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile > index eb60e950ad53334a3ada3db618aa584afb33fb93..f88ba0f71a73cd6935184c8831d6cd6488d6551f 100644 > --- a/drivers/phy/qualcomm/Makefile > +++ b/drivers/phy/qualcomm/Makefile > @@ -5,6 +5,7 @@ obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o > obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o > obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o > obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o > +obj-$(CONFIG_PHY_QCOM_M31_EUSB) += phy-qcom-m31-eusb2.o > obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o > > obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o phy-qcom-qmp-usbc.o > diff --git a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c > new file mode 100644 > index 0000000000000000000000000000000000000000..e15529673e358db914936a60fa605c872cd2511a > --- /dev/null > +++ b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c > @@ -0,0 +1,269 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/phy/phy.h> > +#include <linux/platform_device.h> > +#include <linux/reset.h> > +#include <linux/slab.h> > + > +#define USB_PHY_UTMI_CTRL0 (0x3c) > + > +#define USB_PHY_UTMI_CTRL5 (0x50) > + > +#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) > +#define FSEL (0x7 << 4) > +#define FSEL_38_4_MHZ_VAL (0x6 << 4) > + > +#define USB_PHY_HS_PHY_CTRL2 (0x64) > + > +#define USB_PHY_CFG0 (0x94) > +#define USB_PHY_CFG1 (0x154) > + > +#define USB_PHY_FSEL_SEL (0xb8) > + > +#define USB_PHY_XCFGI_39_32 (0x16c) > +#define USB_PHY_XCFGI_71_64 (0x17c) > +#define USB_PHY_XCFGI_31_24 (0x168) > +#define USB_PHY_XCFGI_7_0 (0x15c) > + > +#define M31_EUSB_PHY_INIT_CFG(o, b, v) \ > +{ \ > + .off = o, \ > + .mask = b, \ > + .val = v, \ > +} > + > +struct m31_phy_tbl_entry { > + u32 off; > + u32 mask; > + u32 val; > +}; > + > +struct m31_eusb2_priv_data { > + const struct m31_phy_tbl_entry *setup_seq; > + unsigned int setup_seq_nregs; > + const struct m31_phy_tbl_entry *override_seq; > + unsigned int override_seq_nregs; > + const struct m31_phy_tbl_entry *reset_seq; > + unsigned int reset_seq_nregs; > + unsigned int fsel; > +}; > + > +static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] = { > + M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, BIT(1), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, BIT(1), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, BIT(0), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_FSEL_SEL, BIT(0), 1), > +}; > + > +static const struct m31_phy_tbl_entry m31_eusb_phy_override_tbl[] = { > + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_39_32, GENMASK(3, 2), 0), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_71_64, GENMASK(3, 0), 7), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_31_24, GENMASK(2, 0), 0), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_7_0, GENMASK(1, 0), 0), > +}; > + > +static const struct m31_phy_tbl_entry m31_eusb_phy_reset_tbl[] = { > + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, BIT(3), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, BIT(2), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL0, BIT(0), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, BIT(1), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, BIT(2), 0), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, BIT(1), 0), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, BIT(3), 0), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, BIT(1), 0), > +}; > + > +struct m31eusb2_phy { > + struct phy *phy; > + void __iomem *base; > + const struct m31_eusb2_priv_data *data; > + > + struct regulator *vreg; > + struct clk *clk; > + struct reset_control *reset; > + > + struct phy *repeater; > +}; > + > +static void msm_m31_eusb2_write_readback(void __iomem *base, u32 offset, > + const u32 mask, u32 val) The function should be named like the other: m31eusb2_phy_write_readback > +{ > + u32 write_val, tmp = readl_relaxed(base + offset); > + > + tmp &= ~mask; > + write_val = tmp | val; > + > + writel_relaxed(write_val, base + offset); > + > + tmp = readl_relaxed(base + offset); > + tmp &= mask; > + > + if (tmp != val) > + pr_err("write: %x to offset: %x FAILED\n", val, offset); Perhaps propagate this error ? > +} > + > +static void m31eusb2_phy_write_sequence(struct m31eusb2_phy *phy, > + const struct m31_phy_tbl_entry *tbl, > + int num) > +{ > + int i; > + > + for (i = 0 ; i < num; i++, tbl++) { > + dev_dbg(&phy->phy->dev, "Offset:%x BitMask:%x Value:%x", > + tbl->off, tbl->mask, tbl->val); > + > + msm_m31_eusb2_write_readback(phy->base, > + tbl->off, tbl->mask, > + tbl->val << __ffs(tbl->mask)); Ditto > + } > +} > + > +static int m31eusb2_phy_init(struct phy *uphy) > +{ > + struct m31eusb2_phy *phy = phy_get_drvdata(uphy); > + const struct m31_eusb2_priv_data *data = phy->data; > + int ret; > + > + ret = regulator_enable(phy->vreg); > + if (ret) { > + dev_err(&uphy->dev, "failed to enable regulator, %d\n", ret); > + return ret; > + } > + > + ret = phy_init(phy->repeater); > + if (ret) { > + dev_err(&uphy->dev, "repeater init failed. %d\n", ret); > + goto disable_vreg; > + } > + > + if (ret) { > + dev_err(&uphy->dev, "failed to enable cfg ahb clock, %d\n", ret); > + goto disable_repeater; > + } Useless code, seems you removed a function call and forgot to remote the error check > + > + /* Perform phy reset */ > + reset_control_assert(phy->reset); > + udelay(5); > + reset_control_deassert(phy->reset); > + > + m31eusb2_phy_write_sequence(phy, data->setup_seq, data->setup_seq_nregs); > + msm_m31_eusb2_write_readback(phy->base, > + USB_PHY_HS_PHY_CTRL_COMMON0, FSEL, > + data->fsel); > + m31eusb2_phy_write_sequence(phy, data->override_seq, data->override_seq_nregs); > + m31eusb2_phy_write_sequence(phy, data->reset_seq, data->reset_seq_nregs); > + > + return 0; > + > +disable_repeater: > + phy_exit(phy->repeater); > +disable_vreg: > + regulator_disable(phy->vreg); > + > + return 0; > +} > + > +static int m31eusb2_phy_exit(struct phy *uphy) > +{ > + struct m31eusb2_phy *phy = phy_get_drvdata(uphy); > + > + regulator_disable(phy->vreg); > + phy_exit(phy->repeater); > + > + return 0; > +} > + > +static const struct phy_ops m31eusb2_phy_gen_ops = { > + .init = m31eusb2_phy_init, > + .exit = m31eusb2_phy_exit, > + .owner = THIS_MODULE, Spurious spaces > +}; > + > +static int m31eusb2_phy_probe(struct platform_device *pdev) > +{ > + struct phy_provider *phy_provider; > + const struct m31_eusb2_priv_data *data; > + struct device *dev = &pdev->dev; > + struct m31eusb2_phy *phy; > + > + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); > + if (!phy) > + return -ENOMEM; > + > + data = of_device_get_match_data(dev); > + if (IS_ERR(data)) > + return -EINVAL; > + phy->data = data; > + > + phy->base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(phy->base)) > + return PTR_ERR(phy->base); > + > + phy->reset = devm_reset_control_get_exclusive_by_index(dev, 0); > + if (IS_ERR(phy->reset)) > + return PTR_ERR(phy->reset); > + > + phy->clk = devm_clk_get(dev, NULL); > + > + phy->phy = devm_phy_create(dev, NULL, &m31eusb2_phy_gen_ops); > + if (IS_ERR(phy->phy)) > + return dev_err_probe(dev, PTR_ERR(phy->phy), > + "failed to create phy\n"); > + > + phy->vreg = devm_regulator_get(dev, "vdd"); > + if (IS_ERR(phy->vreg)) > + return dev_err_probe(dev, PTR_ERR(phy->vreg), > + "failed to get vreg\n"); > + > + phy_set_drvdata(phy->phy, phy); > + > + phy->repeater = devm_of_phy_get_by_index(dev, dev->of_node, 0); > + if (IS_ERR(phy->repeater)) > + return dev_err_probe(dev, PTR_ERR(phy->repeater), > + "failed to get repeater\n"); > + > + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); > + if (!IS_ERR(phy_provider)) > + dev_info(dev, "Registered M31 USB phy\n"); > + > + return PTR_ERR_OR_ZERO(phy_provider); > +} > + > +static const struct m31_eusb2_priv_data m31_eusb_v1_data = { > + .setup_seq = m31_eusb2_setup_tbl, > + .setup_seq_nregs = ARRAY_SIZE(m31_eusb2_setup_tbl), > + .override_seq = m31_eusb_phy_override_tbl, > + .override_seq_nregs = ARRAY_SIZE(m31_eusb_phy_override_tbl), > + .reset_seq = m31_eusb_phy_reset_tbl, > + .reset_seq_nregs = ARRAY_SIZE(m31_eusb_phy_reset_tbl), > + .fsel = FSEL_38_4_MHZ_VAL, > +}; > + > +static const struct of_device_id m31eusb2_phy_id_table[] = { > + { .compatible = "qcom,sm8750-m31-eusb2-phy", .data = &m31_eusb_v1_data }, > + { }, > +}; > +MODULE_DEVICE_TABLE(of, m31eusb2_phy_id_table); > + > +static struct platform_driver m31eusb2_phy_driver = { > + .probe = m31eusb2_phy_probe, > + .driver = { > + .name = "qcom-m31eusb2-phy", > + .of_match_table = m31eusb2_phy_id_table, > + }, > +}; > + > +module_platform_driver(m31eusb2_phy_driver); > + > +MODULE_DESCRIPTION("eUSB2 Qualcomm M31 HSPHY driver"); > +MODULE_LICENSE("GPL"); > Thanks, Neil
On Mon, Jan 13, 2025 at 01:52:08PM -0800, Melody Olvera wrote: > From: Wesley Cheng <quic_wcheng@quicinc.com> > > On SM8750, the M31 eUSB2 PHY is being used to support USB2. Add the > binding definition for the PHY driver. > > Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com> > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > .../bindings/phy/qcom,m31-eusb2-phy.yaml | 84 ++++++++++++++++++++++ > 1 file changed, 84 insertions(+) > > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm8750-gcc.h> > + #include <dt-bindings/clock/qcom,rpmh.h> > + #include <dt-bindings/clock/qcom,sm8750-tcsr.h> This a typical comment, please actually update your internal documentation: don't use GCC's and other clock controller's bindings in examples for other blocks. > + > + usb_1_hsphy: phy@88e3000 { > + compatible = "qcom,sm8750-m31-eusb2-phy"; > + reg = <0x88e3000 0x29c>; > + > + clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + > + #phy-cells = <0>; > + > + vdd-supply = <&vreg_l2d_0p88>; > + vdda12-supply = <&vreg_l3g_1p2>; > + > + }; > > -- > 2.46.1 >
On Mon, Jan 13, 2025 at 01:52:11PM -0800, Melody Olvera wrote: > From: Wesley Cheng <quic_wcheng@quicinc.com> > > On SM8750, the eUSB2 PHY used is M31 based. Add the initialization > sequences to bring it out of reset, and to initialize the associated eUSB2 > repeater as well. What does M31 mean? What is the relationship between the eUSB and USB M31 PHYs? > > Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com> > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > drivers/phy/qualcomm/Kconfig | 12 +- > drivers/phy/qualcomm/Makefile | 1 + > drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 269 ++++++++++++++++++++++++++++++ > 3 files changed, 281 insertions(+), 1 deletion(-) Please run the patch through checkpatch.pl --strict > > diff --git a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c > new file mode 100644 > index 0000000000000000000000000000000000000000..e15529673e358db914936a60fa605c872cd2511a > --- /dev/null > +++ b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c > @@ -0,0 +1,269 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/phy/phy.h> > +#include <linux/platform_device.h> > +#include <linux/reset.h> > +#include <linux/slab.h> > + > +#define USB_PHY_UTMI_CTRL0 (0x3c) > + > +#define USB_PHY_UTMI_CTRL5 (0x50) > + > +#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) > +#define FSEL (0x7 << 4) GENMASK() > +#define FSEL_38_4_MHZ_VAL (0x6 << 4) FIELD_PREP > + > +#define USB_PHY_HS_PHY_CTRL2 (0x64) > + > +#define USB_PHY_CFG0 (0x94) > +#define USB_PHY_CFG1 (0x154) > + > +#define USB_PHY_FSEL_SEL (0xb8) > + > +#define USB_PHY_XCFGI_39_32 (0x16c) > +#define USB_PHY_XCFGI_71_64 (0x17c) > +#define USB_PHY_XCFGI_31_24 (0x168) > +#define USB_PHY_XCFGI_7_0 (0x15c) > + > +#define M31_EUSB_PHY_INIT_CFG(o, b, v) \ > +{ \ > + .off = o, \ > + .mask = b, \ > + .val = v, \ > +} > + > +struct m31_phy_tbl_entry { > + u32 off; > + u32 mask; > + u32 val; > +}; > + > +struct m31_eusb2_priv_data { > + const struct m31_phy_tbl_entry *setup_seq; > + unsigned int setup_seq_nregs; > + const struct m31_phy_tbl_entry *override_seq; > + unsigned int override_seq_nregs; > + const struct m31_phy_tbl_entry *reset_seq; > + unsigned int reset_seq_nregs; > + unsigned int fsel; > +}; > + > +static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] = { > + M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, BIT(1), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, BIT(1), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, BIT(0), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_FSEL_SEL, BIT(0), 1), > +}; > + > +static const struct m31_phy_tbl_entry m31_eusb_phy_override_tbl[] = { > + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_39_32, GENMASK(3, 2), 0), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_71_64, GENMASK(3, 0), 7), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_31_24, GENMASK(2, 0), 0), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_7_0, GENMASK(1, 0), 0), > +}; > + > +static const struct m31_phy_tbl_entry m31_eusb_phy_reset_tbl[] = { > + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, BIT(3), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, BIT(2), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL0, BIT(0), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, BIT(1), 1), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, BIT(2), 0), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, BIT(1), 0), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, BIT(3), 0), > + M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, BIT(1), 0), > +}; > + > +struct m31eusb2_phy { > + struct phy *phy; > + void __iomem *base; > + const struct m31_eusb2_priv_data *data; > + > + struct regulator *vreg; > + struct clk *clk; > + struct reset_control *reset; > + > + struct phy *repeater; > +}; > + > +static void msm_m31_eusb2_write_readback(void __iomem *base, u32 offset, > + const u32 mask, u32 val) > +{ > + u32 write_val, tmp = readl_relaxed(base + offset); > + > + tmp &= ~mask; > + write_val = tmp | val; > + > + writel_relaxed(write_val, base + offset); > + > + tmp = readl_relaxed(base + offset); > + tmp &= mask; > + > + if (tmp != val) > + pr_err("write: %x to offset: %x FAILED\n", val, offset); > +} > + > +static void m31eusb2_phy_write_sequence(struct m31eusb2_phy *phy, > + const struct m31_phy_tbl_entry *tbl, > + int num) > +{ > + int i; > + > + for (i = 0 ; i < num; i++, tbl++) { > + dev_dbg(&phy->phy->dev, "Offset:%x BitMask:%x Value:%x", > + tbl->off, tbl->mask, tbl->val); > + > + msm_m31_eusb2_write_readback(phy->base, > + tbl->off, tbl->mask, > + tbl->val << __ffs(tbl->mask)); could you please check, what actually gets written? I suspect there should be a -1 here. > + } > +} > + > +static int m31eusb2_phy_init(struct phy *uphy) > +{ > + struct m31eusb2_phy *phy = phy_get_drvdata(uphy); > + const struct m31_eusb2_priv_data *data = phy->data; > + int ret; > + > + ret = regulator_enable(phy->vreg); > + if (ret) { > + dev_err(&uphy->dev, "failed to enable regulator, %d\n", ret); > + return ret; > + } > + > + ret = phy_init(phy->repeater); > + if (ret) { > + dev_err(&uphy->dev, "repeater init failed. %d\n", ret); > + goto disable_vreg; > + } > + > + if (ret) { > + dev_err(&uphy->dev, "failed to enable cfg ahb clock, %d\n", ret); > + goto disable_repeater; > + } > + > + /* Perform phy reset */ > + reset_control_assert(phy->reset); > + udelay(5); > + reset_control_deassert(phy->reset); > + > + m31eusb2_phy_write_sequence(phy, data->setup_seq, data->setup_seq_nregs); > + msm_m31_eusb2_write_readback(phy->base, > + USB_PHY_HS_PHY_CTRL_COMMON0, FSEL, > + data->fsel); > + m31eusb2_phy_write_sequence(phy, data->override_seq, data->override_seq_nregs); > + m31eusb2_phy_write_sequence(phy, data->reset_seq, data->reset_seq_nregs); > + > + return 0; > + > +disable_repeater: > + phy_exit(phy->repeater); > +disable_vreg: > + regulator_disable(phy->vreg); > + > + return 0; > +} > +
Add support for the PHYs and controllers used for USB on SM8750 SoCs. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> --- Melody Olvera (1): arm64: defconfig: Add M31 eUSB2 PHY config Wesley Cheng (6): dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8750 to QMP PHY dt-bindings: phy: Add the M31 based eUSB2 PHY bindings dt-bindings: usb: qcom,dwc3: Add SM8750 compatible phy: qcom: qmp-combo: Add new PHY sequences for SM8750 phy: qcom: Add M31 based eUSB2 PHY driver arm64: dts: qcom: sm8750: Add USB support to SM8750 platforms .../bindings/phy/qcom,m31-eusb2-phy.yaml | 84 +++++++ .../phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 2 + .../devicetree/bindings/usb/qcom,dwc3.yaml | 3 + arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 24 ++ arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 24 ++ arch/arm64/boot/dts/qcom/sm8750.dtsi | 134 ++++++++++ arch/arm64/configs/defconfig | 1 + drivers/phy/qualcomm/Kconfig | 12 +- drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 269 +++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 198 +++++++++++++++ 11 files changed, 751 insertions(+), 1 deletion(-) --- base-commit: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc change-id: 20241223-sm8750_usb_master-f27aed7f6d40 Best regards,