| Message ID | 20250110-topic-sm8650-ddr-bw-scaling-v1-2-041d836b084c@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: qcom: sm8650: add DDR, LLCC & L3 CPU bandwidth scaling | expand |
On 10.01.2025 4:21 PM, Neil Armstrong wrote: > Add the OSC L3 Cache controller node. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 86684cb9a9325618ddb74458621cf4bbdc1cc0d1..bc09e879c1440873a52daf3fc7a38f451f1f972c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5506,6 +5506,16 @@ rpmhpd_opp_turbo_l1: opp-416 { }; }; + epss_l3: interconnect@17d90000 { + compatible = "qcom,sm8650-epss-l3", "qcom,epss-l3"; + reg = <0 0x17d90000 0 0x1000>; + + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@17d91000 { compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x17d91000 0 0x1000>,
Add the OSC L3 Cache controller node. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)