@@ -7912,47 +7912,22 @@ TRANS(SUB_ext, do_addsub_ext, a, true, false)
TRANS(ADDS_ext, do_addsub_ext, a, false, true)
TRANS(SUBS_ext, do_addsub_ext, a, true, true)
-/*
- * Add/subtract (shifted register)
- *
- * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
- * +--+--+--+-----------+-----+--+-------+---------+------+------+
- * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
- * +--+--+--+-----------+-----+--+-------+---------+------+------+
- *
- * sf: 0 -> 32bit, 1 -> 64bit
- * op: 0 -> add , 1 -> sub
- * S: 1 -> set flags
- * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
- * imm6: Shift amount to apply to Rm before the add/sub
- */
-static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
+static bool do_addsub_reg(DisasContext *s, arg_addsub_shift *a,
+ bool sub_op, bool setflags)
{
- int rd = extract32(insn, 0, 5);
- int rn = extract32(insn, 5, 5);
- int imm6 = extract32(insn, 10, 6);
- int rm = extract32(insn, 16, 5);
- int shift_type = extract32(insn, 22, 2);
- bool setflags = extract32(insn, 29, 1);
- bool sub_op = extract32(insn, 30, 1);
- bool sf = extract32(insn, 31, 1);
+ TCGv_i64 tcg_rd, tcg_rn, tcg_rm, tcg_result;
- TCGv_i64 tcg_rd = cpu_reg(s, rd);
- TCGv_i64 tcg_rn, tcg_rm;
- TCGv_i64 tcg_result;
-
- if ((shift_type == 3) || (!sf && (imm6 > 31))) {
- unallocated_encoding(s);
- return;
+ if (a->st == 3 || (!a->sf && (a->sa & 32))) {
+ return false;
}
- tcg_rn = read_cpu_reg(s, rn, sf);
- tcg_rm = read_cpu_reg(s, rm, sf);
+ tcg_rd = cpu_reg(s, a->rd);
+ tcg_rn = read_cpu_reg(s, a->rn, a->sf);
+ tcg_rm = read_cpu_reg(s, a->rm, a->sf);
- shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6);
+ shift_reg_imm(tcg_rm, tcg_rm, a->sf, a->st, a->sa);
tcg_result = tcg_temp_new_i64();
-
if (!setflags) {
if (sub_op) {
tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
@@ -7961,19 +7936,25 @@ static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
}
} else {
if (sub_op) {
- gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
+ gen_sub_CC(a->sf, tcg_result, tcg_rn, tcg_rm);
} else {
- gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
+ gen_add_CC(a->sf, tcg_result, tcg_rn, tcg_rm);
}
}
- if (sf) {
+ if (a->sf) {
tcg_gen_mov_i64(tcg_rd, tcg_result);
} else {
tcg_gen_ext32u_i64(tcg_rd, tcg_result);
}
+ return true;
}
+TRANS(ADD_r, do_addsub_reg, a, false, false)
+TRANS(SUB_r, do_addsub_reg, a, true, false)
+TRANS(ADDS_r, do_addsub_reg, a, false, true)
+TRANS(SUBS_r, do_addsub_reg, a, true, true)
+
/* Data-processing (3 source)
*
* 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
@@ -8348,15 +8329,6 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
int op3 = extract32(insn, 10, 6);
if (!op1) {
- if (op2 & 8) {
- if (op2 & 1) {
- goto do_unallocated;
- } else {
- /* Add/sub (shifted register) */
- disas_add_sub_reg(s, insn);
- }
- return;
- }
goto do_unallocated;
}
@@ -718,7 +718,7 @@ XPACD 1 10 11010110 00001 010001 11111 rd:5
# Logical (shifted reg)
&logic_shift rd rn rm sf sa st n
-@logic_shift sf:1 .. ..... st:2 n:1 rm:5 sa:6 rn:5 rd:5
+@logic_shift sf:1 .. ..... st:2 n:1 rm:5 sa:6 rn:5 rd:5 &logic_shift
AND_r . 00 01010 .. . ..... ...... ..... ..... @logic_shift
ORR_r . 01 01010 .. . ..... ...... ..... ..... @logic_shift
@@ -726,6 +726,15 @@ EOR_r . 10 01010 .. . ..... ...... ..... ..... @logic_shift
ANDS_r . 11 01010 .. . ..... ...... ..... ..... @logic_shift
# Add/subtract (shifted reg)
+
+&addsub_shift rd rn rm sf sa st
+@addsub_shift sf:1 .. ..... st:2 . rm:5 sa:6 rn:5 rd:5 &addsub_shift
+
+ADD_r . 00 01011 .. 0 ..... ...... ..... ..... @addsub_shift
+SUB_r . 10 01011 .. 0 ..... ...... ..... ..... @addsub_shift
+ADDS_r . 01 01011 .. 0 ..... ...... ..... ..... @addsub_shift
+SUBS_r . 11 01011 .. 0 ..... ...... ..... ..... @addsub_shift
+
# Add/subtract (extended reg)
&addsub_ext rd rn rm sf sa st
This includes ADD, SUB, ADDS, SUBS (shifted register). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/tcg/translate-a64.c | 64 ++++++++++------------------------ target/arm/tcg/a64.decode | 11 +++++- 2 files changed, 28 insertions(+), 47 deletions(-)