| Message ID | 20241119-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v1-4-54075d75f654@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon | expand |
On 19.11.2024 2:10 PM, Bryan O'Donoghue wrote: > Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration > of previous CAMCC blocks with the exception of having two required > power-domains not just one. > > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..5119cf64b461eb517e9306869ad0ec1b2cae629e 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > +#include <dt-bindings/clock/qcom,x1e80100-camcc.h> > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> > #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> > @@ -4647,6 +4648,22 @@ usb_1_ss1_dwc3_ss: endpoint { > }; > }; > > + camcc: clock-controller@ade0000 { > + compatible = "qcom,x1e80100-camcc"; > + reg = <0 0x0ade0000 0 0x20000>; > + clocks = <&gcc GCC_CAMERA_AHB_CLK>, This clock is not registered with the CCF Konrad
On Mon, Dec 02, 2024 at 03:27:11PM +0100, Konrad Dybcio wrote: > On 19.11.2024 2:10 PM, Bryan O'Donoghue wrote: > > Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration > > of previous CAMCC blocks with the exception of having two required > > power-domains not just one. > > > > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 17 +++++++++++++++++ > > 1 file changed, 17 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..5119cf64b461eb517e9306869ad0ec1b2cae629e 100644 > > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > @@ -3,6 +3,7 @@ > > * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > > */ > > > > +#include <dt-bindings/clock/qcom,x1e80100-camcc.h> > > #include <dt-bindings/clock/qcom,rpmh.h> > > #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> > > #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> > > @@ -4647,6 +4648,22 @@ usb_1_ss1_dwc3_ss: endpoint { > > }; > > }; > > > > + camcc: clock-controller@ade0000 { > > + compatible = "qcom,x1e80100-camcc"; > > + reg = <0 0x0ade0000 0 0x20000>; > > + clocks = <&gcc GCC_CAMERA_AHB_CLK>, > > This clock is not registered with the CCF Isn't that be going to be handled by the CCF on its own (like orphans, etc)?
On 02/12/2024 15:02, Dmitry Baryshkov wrote: >>> + clocks = <&gcc GCC_CAMERA_AHB_CLK>, >> This clock is not registered with the CCF > Isn't that be going to be handled by the CCF on its own (like orphans, > etc)? For refence this is always-on ATM. drivers/clk/qcom/gcc-x1e80100.c: qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ --- bod
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..5119cf64b461eb517e9306869ad0ec1b2cae629e 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include <dt-bindings/clock/qcom,x1e80100-camcc.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> @@ -4647,6 +4648,22 @@ usb_1_ss1_dwc3_ss: endpoint { }; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,x1e80100-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + status = "disabled"; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,x1e80100-mdss"; reg = <0 0x0ae00000 0 0x1000>;
Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration of previous CAMCC blocks with the exception of having two required power-domains not just one. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)