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[v5,0/5] Add initial support for QCS615 SoC and QCS615 RIDE board

Message ID 20241104-add_initial_support_for_qcs615-v5-0-9dde8d7b80b0@quicinc.com
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Series Add initial support for QCS615 SoC and QCS615 RIDE board | expand

Message

Lijuan Gao Nov. 4, 2024, 9:10 a.m. UTC 
Introduces the Device Tree for the QCS615 platform.

Features added and enabled:
- CPUs with PSCI idle states
- Interrupt-controller with PDC wakeup support
- Timers, TCSR Clock Controllers
- Reserved Shared memory
- QFPROM
- TLMM
- Watchdog
- RPMH controller
- Sleep stats driver
- Rpmhpd power controller
- Interconnect
- GCC and Rpmhcc
- QUP with Uart serial support

Bindings and base Device Tree for the QCS615 SoC are splited
in four parts:
- 1-2: Binding files for QCS615 SoC and PDC (Reviewed)
- 3-4: Initial DTSI and RIDE board device tree
- 5  : Enable uart related configs

Bindings Dependencies:
- watchdog: https://lore.kernel.org/all/20240920-add_watchdog_compatible_for_qcs615-v2-1-427944f1151e@quicinc.com/ - Reviewed
- qfprom: https://lore.kernel.org/all/20240912-add_qfprom_compatible_for_qcs615-v1-1-9ef2e26c14ee@quicinc.com/ - Reviewed
- tcsr: https://lore.kernel.org/all/20240920-add_tcsr_compatible_for_qcs615-v2-1-8ce2dbc7f72c@quicinc.com/ - Applied
- tlmm: https://lore.kernel.org/all/20240920-add_qcs615_pinctrl_driver-v2-1-e03c42a9d055@quicinc.com/ - Applied
- interconnect: https://lore.kernel.org/all/20240924143958.25-2-quic_rlaggysh@quicinc.com/ - Applied
- rpmhcc: https://lore.kernel.org/all/20241022-qcs615-clock-driver-v4-1-3d716ad0d987@quicinc.com/  - Reviewed
- gcc: https://lore.kernel.org/all/20241022-qcs615-clock-driver-v4-3-3d716ad0d987@quicinc.com/ - Reviewed
- rpmhpd: https://lore.kernel.org/all/20240927-add_qcs615_qcs8300_powerdomains_driver_support-v2-3-18c030ad7b68@quicinc.com/ - Applied

Build Dependencies:
- tlmm: https://lore.kernel.org/all/20240920-add_qcs615_pinctrl_driver-v2-2-e03c42a9d055@quicinc.com/ - Applied
- rpmhcc: https://lore.kernel.org/all/20241022-qcs615-clock-driver-v4-2-3d716ad0d987@quicinc.com/ - Reviewed
- gcc: https://lore.kernel.org/all/20241022-qcs615-clock-driver-v4-4-3d716ad0d987@quicinc.com/

Patch made the following verifications:
- Successfully passed dt_binding_check with DT_CHECKER_FLAGS=-m for earch binding file
- Successfully passed dtbs_check with W=1 for dts
- Verified CPU Hotplug, idle and online CPUs on QCS615 ride board
- Checked pinctrl-maps path
- Verified watchdog functionality with "echo 1 > /dev/watchdog", can trigger
  a watchdog bark and later bite
- Verified functionality with UART console on QCS615 ride board
- RPMH controller driver probed successfully
- Sleep stats driver probed successfully and checked qcom_stats
  node on QCS615 ride board

Signed-off-by: lijuang <quic_lijuang@quicinc.com>
---
Changes in v5:
- Remove applied patches 2 and 4
- Update the titles and commit messages of the initial DTSI and ride DTS
- Update the commit message of defconfig patch
- Pad register addresses to 8 hex digits
- Link to v4: https://lore.kernel.org/r/20241022-add_initial_support_for_qcs615-v4-0-0a551c6dd342@quicinc.com

Changes in v4:
- Configure vreg_l17a to High Power Mode (HPM) as it supplies power to UFS
  and eMMC, which can be utilized as boot devices.
- Link to v3: https://lore.kernel.org/r/20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com

Changes in v3:
- Added interconnect, GCC, RPMHCC, QPU, and RPMHPD related nodes for UART console
- Enabled UART condole on ride board device
- Link to v2: https://lore.kernel.org/r/20240913-add_initial_support_for_qcs615-v2-0-9236223e7dab@quicinc.com

Changes in v2:
- Collected reviewed-bys
- Removed extra blank line
- Removed redundant function
- Renamed xo-board to xo-board-clk and move it and sleep-clk to board dts
- Renamed system-sleep to cluster_sleep_2
- Removed cluster1
- Added entry-method for idle-states
- Added DTS chassis type
- Added TCSR Clock Controllers
- Added Reserved Shared memory
- Added QFPROM
- Added TLMM
- Added Watchdog
- Added RPMH controller
- Added Sleep stats driver
- Link to v1: https://lore.kernel.org/r/20240828-add_initial_support_for_qcs615-v1-0-5599869ea10f@quicinc.com

---
Lijuan Gao (5):
      dt-bindings: arm: qcom: document QCS615 and the reference board
      dt-bindings: qcom,pdc: document QCS615 Power Domain Controller
      arm64: dts: qcom: add QCS615 platform
      arm64: dts: qcom: add base QCS615 RIDE
      arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS615

 Documentation/devicetree/bindings/arm/qcom.yaml    |   6 +
 .../bindings/interrupt-controller/qcom,pdc.yaml    |   1 +
 arch/arm64/boot/dts/qcom/Makefile                  |   1 +
 arch/arm64/boot/dts/qcom/qcs615-ride.dts           | 219 +++++++
 arch/arm64/boot/dts/qcom/qcs615.dtsi               | 688 +++++++++++++++++++++
 arch/arm64/configs/defconfig                       |   3 +
 6 files changed, 918 insertions(+)
---
base-commit: ec29543c01b3dbfcb9a2daa4e0cd33afb3c30c39
change-id: 20241104-add_initial_support_for_qcs615-6045c281925b
prerequisite-change-id: 20240919-qcs615-clock-driver-d74abed69854:v4
prerequisite-patch-id: cd9fc0a399ab430e293764d0911a38109664ca91
prerequisite-patch-id: 07f2c7378c7bbd560f26b61785b6814270647f1b
prerequisite-patch-id: a57054b890d767b45cca87e71b4a0f6bf6914c2f
prerequisite-patch-id: 5a8e9ea15a2c3d60b4dbdf11b4e2695742d6333c
prerequisite-change-id: 20240920-add_watchdog_compatible_for_qcs615-eec8a8c2c924:v2
prerequisite-patch-id: 3a76212d3a3e930d771312ff9349f87aee5c55d5
prerequisite-change-id: 20240911-add_qfprom_compatible_for_qcs615-e3b02f6fa71e:v1
prerequisite-patch-id: 8a2454d5e07e56a6dd03f762f498051065635d85

Best regards,

Comments

Bjorn Andersson Dec. 2, 2024, 3:51 p.m. UTC | #1 
On Mon, 04 Nov 2024 17:10:07 +0800, Lijuan Gao wrote:
> Introduces the Device Tree for the QCS615 platform.
> 
> Features added and enabled:
> - CPUs with PSCI idle states
> - Interrupt-controller with PDC wakeup support
> - Timers, TCSR Clock Controllers
> - Reserved Shared memory
> - QFPROM
> - TLMM
> - Watchdog
> - RPMH controller
> - Sleep stats driver
> - Rpmhpd power controller
> - Interconnect
> - GCC and Rpmhcc
> - QUP with Uart serial support
> 
> [...]

Applied, thanks!

[5/5] arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS615
      commit: 9eec6ce36b5dc981327e9f58025d012e524687b4

Best regards,