diff mbox series

[v3,15/16] target/mips: Convert MIPS16e LI opcodes to decodetree

Message ID 20241126140003.74871-16-philmd@linaro.org
State New
Headers show
Series target/mips: Convert nanoMIPS LSA opcode to decodetree | expand

Commit Message

Philippe Mathieu-Daudé Nov. 26, 2024, 2 p.m. UTC 
Decode the destination register using the xlat() helper.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/mips16e_16.decode       |  8 ++++++++
 target/mips/tcg/mips16e_32.decode       |  9 +++++++++
 target/mips/tcg/mips16e_translate.c     | 14 ++++++++++++++
 target/mips/tcg/mips16e_translate.c.inc | 11 -----------
 4 files changed, 31 insertions(+), 11 deletions(-)

Comments

Richard Henderson Nov. 26, 2024, 9:55 p.m. UTC | #1 
On 11/26/24 08:00, Philippe Mathieu-Daudé wrote:
> Decode the destination register using the xlat() helper.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/tcg/mips16e_16.decode       |  8 ++++++++
>   target/mips/tcg/mips16e_32.decode       |  9 +++++++++
>   target/mips/tcg/mips16e_translate.c     | 14 ++++++++++++++
>   target/mips/tcg/mips16e_translate.c.inc | 11 -----------
>   4 files changed, 31 insertions(+), 11 deletions(-)
> 
> diff --git a/target/mips/tcg/mips16e_16.decode b/target/mips/tcg/mips16e_16.decode
> index 82586493f68..bae7bfbb522 100644
> --- a/target/mips/tcg/mips16e_16.decode
> +++ b/target/mips/tcg/mips16e_16.decode
> @@ -7,3 +7,11 @@
>   # Reference: MIPS Architecture for Programmers, Volume IV-a
>   #            The MIPS16e Application Specific Extension
>   #            (Document Number: MD00076)
> +
> +&rd_imm         rd imm
> +
> +%xlat_rx8       8:3  !function=xlat
> +
> +@ri             ..... ... imm:8             &rd_imm   rd=%xlat_rx8

mips16e is decent enough to name its instruction formats -- this one is "I8".  You'd do 
well to use those names.


> +
> +LI              01101 ... ........          @ri
> diff --git a/target/mips/tcg/mips16e_32.decode b/target/mips/tcg/mips16e_32.decode
> index fc429049e18..248ee95706d 100644
> --- a/target/mips/tcg/mips16e_32.decode
> +++ b/target/mips/tcg/mips16e_32.decode
> @@ -7,3 +7,12 @@
>   # Reference: MIPS Architecture for Programmers, Volume IV-a
>   #            The MIPS16e Application Specific Extension
>   #            (Document Number: MD00076)
> +
> +&rd_imm         rd imm                                          !extern
> +
> +%immx           0:5 21:6 16:5

The bits are in reverse order.

> +%xlat_rx8       8:3  !function=xlat
> +
> +@ri             ..... ...... ..... ..... ... ... .....          &rd_imm rd=%xlat_rx8 imm=%immx

The format is "EXT-I8", though there appear to be variants where the immediate is signed 
(ADDIU) or unsigned (LI).

> @@ -9,6 +9,20 @@
>   #include "qemu/osdep.h"
>   #include "translate.h"
>   
> +static inline int xlat(DisasContext *ctx, int x)
> +{
> +  static const int map[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
> +
> +  return map[x];
> +}

Don't mark inline.

> +
>   /* Include the auto-generated decoders.  */
>   #include "decode-mips16e_16.c.inc"
>   #include "decode-mips16e_32.c.inc"
> +
> +static bool trans_LI(DisasContext *ctx, arg_rd_imm *a)
> +{
> +    gen_li(ctx, a->rd, a->imm);
> +
> +    return true;
> +}

We nearly have the right set of decodetree options to allow these trans_* functions to be 
shared:

     --translate=trans

which will drop the 'static'.  But we do not currently have an option to emit a separate 
header with all of the declarations.  That should be trivial.


r~
diff mbox series

Patch

diff --git a/target/mips/tcg/mips16e_16.decode b/target/mips/tcg/mips16e_16.decode
index 82586493f68..bae7bfbb522 100644
--- a/target/mips/tcg/mips16e_16.decode
+++ b/target/mips/tcg/mips16e_16.decode
@@ -7,3 +7,11 @@ 
 # Reference: MIPS Architecture for Programmers, Volume IV-a
 #            The MIPS16e Application Specific Extension
 #            (Document Number: MD00076)
+
+&rd_imm         rd imm
+
+%xlat_rx8       8:3  !function=xlat
+
+@ri             ..... ... imm:8             &rd_imm   rd=%xlat_rx8
+
+LI              01101 ... ........          @ri
diff --git a/target/mips/tcg/mips16e_32.decode b/target/mips/tcg/mips16e_32.decode
index fc429049e18..248ee95706d 100644
--- a/target/mips/tcg/mips16e_32.decode
+++ b/target/mips/tcg/mips16e_32.decode
@@ -7,3 +7,12 @@ 
 # Reference: MIPS Architecture for Programmers, Volume IV-a
 #            The MIPS16e Application Specific Extension
 #            (Document Number: MD00076)
+
+&rd_imm         rd imm                                          !extern
+
+%immx           0:5 21:6 16:5
+%xlat_rx8       8:3  !function=xlat
+
+@ri             ..... ...... ..... ..... ... ... .....          &rd_imm rd=%xlat_rx8 imm=%immx
+
+LI              11110 ...... ..... 01101 ... 000 .....          @ri
diff --git a/target/mips/tcg/mips16e_translate.c b/target/mips/tcg/mips16e_translate.c
index 6de9928b37e..a66f49fe8ed 100644
--- a/target/mips/tcg/mips16e_translate.c
+++ b/target/mips/tcg/mips16e_translate.c
@@ -9,6 +9,20 @@ 
 #include "qemu/osdep.h"
 #include "translate.h"
 
+static inline int xlat(DisasContext *ctx, int x)
+{
+  static const int map[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
+
+  return map[x];
+}
+
 /* Include the auto-generated decoders.  */
 #include "decode-mips16e_16.c.inc"
 #include "decode-mips16e_32.c.inc"
+
+static bool trans_LI(DisasContext *ctx, arg_rd_imm *a)
+{
+    gen_li(ctx, a->rd, a->imm);
+
+    return true;
+}
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index a57ae4e95b1..f3f09b164ae 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -24,7 +24,6 @@  enum {
   M16_OPC_SLTI = 0x0a,
   M16_OPC_SLTIU = 0x0b,
   M16_OPC_I8 = 0x0c,
-  M16_OPC_LI = 0x0d,
   M16_OPC_CMPI = 0x0e,
   M16_OPC_SD = 0x0f,
   M16_OPC_LB = 0x10,
@@ -582,9 +581,6 @@  static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
             break;
         }
         break;
-    case M16_OPC_LI:
-        tcg_gen_movi_tl(cpu_gpr[rx], (uint16_t) imm);
-        break;
     case M16_OPC_CMPI:
         tcg_gen_xori_tl(cpu_gpr[24], cpu_gpr[rx], (uint16_t) imm);
         break;
@@ -839,13 +835,6 @@  static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
             }
         }
         break;
-    case M16_OPC_LI:
-        {
-            int16_t imm = (uint8_t) ctx->opcode;
-
-            gen_arith_imm(ctx, OPC_ADDIU, rx, 0, imm);
-        }
-        break;
     case M16_OPC_CMPI:
         {
             int16_t imm = (uint8_t) ctx->opcode;