@@ -248,6 +248,7 @@
#define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */
#define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */
#define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */
+#define MSDC_PB2_POP_EN_CNT GENMASK(23, 20) /* RW */
#define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */
#define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */
@@ -403,6 +404,8 @@ struct mtk_mmc_compatible {
bool data_tune;
bool busy_check;
bool stop_clk_fix;
+ u8 stop_dly_sel;
+ u8 pop_en_cnt;
bool enhance_rx;
bool support_64g;
bool use_internal_cd;
@@ -504,6 +507,7 @@ static const struct mtk_mmc_compatible mt2712_compat = {
.data_tune = true,
.busy_check = true,
.stop_clk_fix = true,
+ .stop_dly_sel = 3,
.enhance_rx = true,
.support_64g = true,
};
@@ -517,6 +521,7 @@ static const struct mtk_mmc_compatible mt6779_compat = {
.data_tune = true,
.busy_check = true,
.stop_clk_fix = true,
+ .stop_dly_sel = 3,
.enhance_rx = true,
.support_64g = true,
};
@@ -556,6 +561,7 @@ static const struct mtk_mmc_compatible mt7622_compat = {
.data_tune = true,
.busy_check = true,
.stop_clk_fix = true,
+ .stop_dly_sel = 3,
.enhance_rx = true,
.support_64g = false,
};
@@ -569,6 +575,7 @@ static const struct mtk_mmc_compatible mt7986_compat = {
.data_tune = true,
.busy_check = true,
.stop_clk_fix = true,
+ .stop_dly_sel = 3,
.enhance_rx = true,
.support_64g = true,
};
@@ -608,6 +615,7 @@ static const struct mtk_mmc_compatible mt8183_compat = {
.data_tune = true,
.busy_check = true,
.stop_clk_fix = true,
+ .stop_dly_sel = 3,
.enhance_rx = true,
.support_64g = true,
};
@@ -621,6 +629,7 @@ static const struct mtk_mmc_compatible mt8516_compat = {
.data_tune = true,
.busy_check = true,
.stop_clk_fix = true,
+ .stop_dly_sel = 3,
};
static const struct of_device_id msdc_of_ids[] = {
@@ -1767,8 +1776,16 @@ static void msdc_init_hw(struct msdc_host *host)
sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
if (host->dev_comp->stop_clk_fix) {
- sdr_set_field(host->base + MSDC_PATCH_BIT1,
- MSDC_PATCH_BIT1_STOP_DLY, 3);
+ if (host->dev_comp->stop_dly_sel)
+ sdr_set_field(host->base + MSDC_PATCH_BIT1,
+ MSDC_PATCH_BIT1_STOP_DLY,
+ host->dev_comp->stop_dly_sel);
+
+ if (host->dev_comp->pop_en_cnt)
+ sdr_set_field(host->base + MSDC_PATCH_BIT2,
+ MSDC_PB2_POP_EN_CNT,
+ host->dev_comp->pop_en_cnt);
+
sdr_clr_bits(host->base + SDC_FIFO_CFG,
SDC_FIFO_CFG_WRVALIDSEL);
sdr_clr_bits(host->base + SDC_FIFO_CFG,
There are modified register settings for STOP_DLY_SEL and POP_EN_CNT from our next generation SoCs, due to the advanced chip manufacturing process and the resulting changes in the internal signal timing. Add two new fields to the compatibility structure to reflect the modifications. For legacy SoCs, also add the original value of 'stop_dly_sel' to the platform data, for unified code setting. Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.com> --- drivers/mmc/host/mtk-sd.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-)