| Message ID | 20240930111859.22264-3-v.pavani@samsung.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/2] clk: samsung: Use samsung CCF common function | expand |
On 30/09/2024 13:18, Varada Pavani wrote: > Add PLL locktime for PLL142XX controller. > So you send the same? Or something new? Please provide proper changelog and mark patches as v2/v3 or RESEND. But anyway this cannot be RESEND as I explicitly asked for fixing. <form letter> This is a friendly reminder during the review process. It seems my or other reviewer's previous comments were not fully addressed. Maybe the feedback got lost between the quotes, maybe you just forgot to apply it. Please go back to the previous discussion and either implement all requested changes or keep discussing them. Thank you. </form letter> Best regards, Krzysztof
> -----Original Message----- > From: Krzysztof Kozlowski [mailto:krzk@kernel.org] > Sent: 30 September 2024 18:05 > To: Varada Pavani <v.pavani@samsung.com>; s.nawrocki@samsung.com; > cw00.choi@samsung.com; alim.akhtar@samsung.com; > mturquette@baylibre.com; sboyd@kernel.org; linux-samsung- > soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > Cc: aswani.reddy@samsung.com; pankaj.dubey@samsung.com; > gost.dev@samsung.com; stable@vger.kernel.org > Subject: Re: [PATCH 2/2] clk: samsung: Fixes PLL locktime for PLL142XX used > on FSD platfom > > On 30/09/2024 13:18, Varada Pavani wrote: > > Add PLL locktime for PLL142XX controller. > > > > So you send the same? Or something new? Please provide proper changelog > and mark patches as v2/v3 or RESEND. > > But anyway this cannot be RESEND as I explicitly asked for fixing. > > <form letter> > This is a friendly reminder during the review process. > > It seems my or other reviewer's previous comments were not fully > addressed. Maybe the feedback got lost between the quotes, maybe you > just forgot to apply it. Please go back to the previous discussion and either > implement all requested changes or keep discussing them. > > Thank you. > </form letter> > > Best regards, > Krzysztof Sorry, have sent the same patch again. As I need to post one patch alone which got missed due to internal technical issue. Next time onwards will make sure to mark the patches as V2/V3 or RESEND accordingly. Regards, Varada Pavani
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 4be879ab917e..d4c5ae20de4f 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -206,6 +206,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = { */ /* Maximum lock time can be 270 * PDIV cycles */ #define PLL35XX_LOCK_FACTOR (270) +#define PLL142XX_LOCK_FACTOR (150) #define PLL35XX_MDIV_MASK (0x3FF) #define PLL35XX_PDIV_MASK (0x3F) @@ -272,7 +273,11 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, } /* Set PLL lock time. */ - writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, + if (pll->type == pll_142xx) + writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR, + pll->lock_reg); + else + writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, pll->lock_reg); /* Change PLL PMS values */
Add PLL locktime for PLL142XX controller. Fixes: 4f346005aaed ("clk: samsung: fsd: Add initial clock support") Cc: stable@vger.kernel.org Signed-off-by: Varada Pavani <v.pavani@samsung.com> --- drivers/clk/samsung/clk-pll.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)