diff mbox series

[v2,09/13] ufs: Sync possible UFS Quirks with Linux UFS driver

Message ID 20240920-topic-ufs-enhancements-v2-9-65ae61e73eaa@linaro.org
State New
Headers show
Series ufs: enhancements to support Qualcomm UFS controllers | expand

Commit Message

Neil Armstrong Sept. 20, 2024, 8 a.m. UTC
From: Bhupesh Sharma <bhupesh.linux@gmail.com>

Sync u-boot UFS driver to add all possible UFS Quirks
as supported by Linux UFS driver as well.

Synced with include/ufs/ufshcd.h from Linux v6.11 release

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Tested-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
---
 drivers/ufs/ufs.h | 193 +++++++++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 162 insertions(+), 31 deletions(-)

Comments

Neil Armstrong Sept. 20, 2024, 8:04 a.m. UTC | #1
On 20/09/2024 10:00, neil.armstrong@linaro.org wrote:
> From: Bhupesh Sharma <bhupesh.linux@gmail.com>
> 
> Sync u-boot UFS driver to add all possible UFS Quirks
> as supported by Linux UFS driver as well.
> 
> Synced with include/ufs/ufshcd.h from Linux v6.11 release
> 
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> Tested-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
> ---
>   drivers/ufs/ufs.h | 193 +++++++++++++++++++++++++++++++++++++++++++++---------
>   1 file changed, 162 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h
> index 555f8a6857d..a1006b80e88 100644
> --- a/drivers/ufs/ufs.h
> +++ b/drivers/ufs/ufs.h
> @@ -712,38 +712,169 @@ struct ufs_hba {
>   	u32			version;
>   	u32			intr_mask;
>   	u32			quirks;
> -/*
> - * If UFS host controller is having issue in processing LCC (Line
> - * Control Command) coming from device then enable this quirk.
> - * When this quirk is enabled, host controller driver should disable
> - * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
> - * attribute of device to 0).
> - */
> -#define UFSHCD_QUIRK_BROKEN_LCC				BIT(0)
> -
> -/*
> - * This quirk needs to be enabled if the host controller has
> - * 64-bit addressing supported capability but it doesn't work.
> - */
> -#define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS		BIT(1)
> -
> -/*
> - * This quirk needs to be enabled if the host controller has
> - * auto-hibernate capability but it's FASTAUTO only.
> - */
> -#define UFSHCD_QUIRK_HIBERN_FASTAUTO			BIT(2)
> -
> -/*
> - * This quirk needs to be enabled if the host controller has
> - * 64-bit addressing supported capability but it doesn't work.
> - */
> -#define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS		0x2
>   
> -/*
> - * This quirk needs to be enabled if the host controller has
> - * auto-hibernate capability but it's FASTAUTO only.
> - */
> -#define UFSHCD_QUIRK_HIBERN_FASTAUTO			0x4
> +enum ufshcd_quirks {
> +	/* Interrupt aggregation support is broken */
> +	UFSHCD_QUIRK_BROKEN_INTR_AGGR			= 1 << 0,
> +
> +	/*
> +	 * delay before each dme command is required as the unipro
> +	 * layer has shown instabilities
> +	 */
> +	UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS		= 1 << 1,
> +
> +	/*
> +	 * If UFS host controller is having issue in processing LCC (Line
> +	 * Control Command) coming from device then enable this quirk.
> +	 * When this quirk is enabled, host controller driver should disable
> +	 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
> +	 * attribute of device to 0).
> +	 */
> +	UFSHCD_QUIRK_BROKEN_LCC				= 1 << 2,
> +
> +	/*
> +	 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
> +	 * inbound Link supports unterminated line in HS mode. Setting this
> +	 * attribute to 1 fixes moving to HS gear.
> +	 */
> +	UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP		= 1 << 3,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller only allows
> +	 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
> +	 * SLOW AUTO).
> +	 */
> +	UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE		= 1 << 4,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller doesn't
> +	 * advertise the correct version in UFS_VER register. If this quirk
> +	 * is enabled, standard UFS host driver will call the vendor specific
> +	 * ops (get_ufs_hci_version) to get the correct version.
> +	 */
> +	UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION		= 1 << 5,
> +
> +	/*
> +	 * Clear handling for transfer/task request list is just opposite.
> +	 */
> +	UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR		= 1 << 6,
> +
> +	/*
> +	 * This quirk needs to be enabled if host controller doesn't allow
> +	 * that the interrupt aggregation timer and counter are reset by s/w.
> +	 */
> +	UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR		= 1 << 7,
> +
> +	/*
> +	 * This quirks needs to be enabled if host controller cannot be
> +	 * enabled via HCE register.
> +	 */
> +	UFSHCI_QUIRK_BROKEN_HCE				= 1 << 8,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller regards
> +	 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
> +	 */
> +	UFSHCD_QUIRK_PRDT_BYTE_GRAN			= 1 << 9,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller reports
> +	 * OCS FATAL ERROR with device error through sense data
> +	 */
> +	UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR		= 1 << 10,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller has
> +	 * auto-hibernate capability but it doesn't work.
> +	 */
> +	UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8		= 1 << 11,
> +
> +	/*
> +	 * This quirk needs to disable manual flush for write booster
> +	 */
> +	UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL		= 1 << 12,
> +
> +	/*
> +	 * This quirk needs to disable unipro timeout values
> +	 * before power mode change
> +	 */
> +	UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller does not
> +	 * support UIC command
> +	 */
> +	UFSHCD_QUIRK_BROKEN_UIC_CMD			= 1 << 15,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller cannot
> +	 * support physical host configuration.
> +	 */
> +	UFSHCD_QUIRK_SKIP_PH_CONFIGURATION		= 1 << 16,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller has
> +	 * 64-bit addressing supported capability but it doesn't work.
> +	 */
> +	UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS		= 1 << 17,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller has
> +	 * auto-hibernate capability but it's FASTAUTO only.
> +	 */
> +	UFSHCD_QUIRK_HIBERN_FASTAUTO			= 1 << 18,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller needs
> +	 * to reinit the device after switching to maximum gear.
> +	 */
> +	UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH       = 1 << 19,
> +
> +	/*
> +	 * Some host raises interrupt (per queue) in addition to
> +	 * CQES (traditional) when ESI is disabled.
> +	 * Enable this quirk will disable CQES and use per queue interrupt.
> +	 */
> +	UFSHCD_QUIRK_MCQ_BROKEN_INTR			= 1 << 20,
> +
> +	/*
> +	 * Some host does not implement SQ Run Time Command (SQRTC) register
> +	 * thus need this quirk to skip related flow.
> +	 */
> +	UFSHCD_QUIRK_MCQ_BROKEN_RTC			= 1 << 21,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller supports inline
> +	 * encryption but it needs to initialize the crypto capabilities in a
> +	 * nonstandard way and/or needs to override blk_crypto_ll_ops.  If
> +	 * enabled, the standard code won't initialize the blk_crypto_profile;
> +	 * ufs_hba_variant_ops::init() must do it instead.
> +	 */
> +	UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE		= 1 << 22,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller supports inline
> +	 * encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e.
> +	 * host controller initialization fails if that bit is set.
> +	 */
> +	UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE		= 1 << 23,
> +
> +	/*
> +	 * This quirk needs to be enabled if the host controller driver copies
> +	 * cryptographic keys into the PRDT in order to send them to hardware,
> +	 * and therefore the PRDT should be zeroized after each request (as per
> +	 * the standard best practice for managing keys).
> +	 */
> +	UFSHCD_QUIRK_KEYS_IN_PRDT			= 1 << 24,
> +
> +	/*
> +	 * This quirk indicates that the controller reports the value 1 (not
> +	 * supported) in the Legacy Single DoorBell Support (LSDBS) bit of the
> +	 * Controller Capabilities register although it supports the legacy
> +	 * single doorbell mode.
> +	 */
> +	UFSHCD_QUIRK_BROKEN_LSDBS_CAP			= 1 << 25,
> +};
>   
>   	/* Virtual memory reference */
>   	struct utp_transfer_cmd_desc *ucdl;
> 

Ignore this patch, it's broken... I'll fix it in v3

Neil
diff mbox series

Patch

diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h
index 555f8a6857d..a1006b80e88 100644
--- a/drivers/ufs/ufs.h
+++ b/drivers/ufs/ufs.h
@@ -712,38 +712,169 @@  struct ufs_hba {
 	u32			version;
 	u32			intr_mask;
 	u32			quirks;
-/*
- * If UFS host controller is having issue in processing LCC (Line
- * Control Command) coming from device then enable this quirk.
- * When this quirk is enabled, host controller driver should disable
- * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
- * attribute of device to 0).
- */
-#define UFSHCD_QUIRK_BROKEN_LCC				BIT(0)
-
-/*
- * This quirk needs to be enabled if the host controller has
- * 64-bit addressing supported capability but it doesn't work.
- */
-#define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS		BIT(1)
-
-/*
- * This quirk needs to be enabled if the host controller has
- * auto-hibernate capability but it's FASTAUTO only.
- */
-#define UFSHCD_QUIRK_HIBERN_FASTAUTO			BIT(2)
-
-/*
- * This quirk needs to be enabled if the host controller has
- * 64-bit addressing supported capability but it doesn't work.
- */
-#define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS		0x2
 
-/*
- * This quirk needs to be enabled if the host controller has
- * auto-hibernate capability but it's FASTAUTO only.
- */
-#define UFSHCD_QUIRK_HIBERN_FASTAUTO			0x4
+enum ufshcd_quirks {
+	/* Interrupt aggregation support is broken */
+	UFSHCD_QUIRK_BROKEN_INTR_AGGR			= 1 << 0,
+
+	/*
+	 * delay before each dme command is required as the unipro
+	 * layer has shown instabilities
+	 */
+	UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS		= 1 << 1,
+
+	/*
+	 * If UFS host controller is having issue in processing LCC (Line
+	 * Control Command) coming from device then enable this quirk.
+	 * When this quirk is enabled, host controller driver should disable
+	 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
+	 * attribute of device to 0).
+	 */
+	UFSHCD_QUIRK_BROKEN_LCC				= 1 << 2,
+
+	/*
+	 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
+	 * inbound Link supports unterminated line in HS mode. Setting this
+	 * attribute to 1 fixes moving to HS gear.
+	 */
+	UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP		= 1 << 3,
+
+	/*
+	 * This quirk needs to be enabled if the host controller only allows
+	 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
+	 * SLOW AUTO).
+	 */
+	UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE		= 1 << 4,
+
+	/*
+	 * This quirk needs to be enabled if the host controller doesn't
+	 * advertise the correct version in UFS_VER register. If this quirk
+	 * is enabled, standard UFS host driver will call the vendor specific
+	 * ops (get_ufs_hci_version) to get the correct version.
+	 */
+	UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION		= 1 << 5,
+
+	/*
+	 * Clear handling for transfer/task request list is just opposite.
+	 */
+	UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR		= 1 << 6,
+
+	/*
+	 * This quirk needs to be enabled if host controller doesn't allow
+	 * that the interrupt aggregation timer and counter are reset by s/w.
+	 */
+	UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR		= 1 << 7,
+
+	/*
+	 * This quirks needs to be enabled if host controller cannot be
+	 * enabled via HCE register.
+	 */
+	UFSHCI_QUIRK_BROKEN_HCE				= 1 << 8,
+
+	/*
+	 * This quirk needs to be enabled if the host controller regards
+	 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
+	 */
+	UFSHCD_QUIRK_PRDT_BYTE_GRAN			= 1 << 9,
+
+	/*
+	 * This quirk needs to be enabled if the host controller reports
+	 * OCS FATAL ERROR with device error through sense data
+	 */
+	UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR		= 1 << 10,
+
+	/*
+	 * This quirk needs to be enabled if the host controller has
+	 * auto-hibernate capability but it doesn't work.
+	 */
+	UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8		= 1 << 11,
+
+	/*
+	 * This quirk needs to disable manual flush for write booster
+	 */
+	UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL		= 1 << 12,
+
+	/*
+	 * This quirk needs to disable unipro timeout values
+	 * before power mode change
+	 */
+	UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
+
+	/*
+	 * This quirk needs to be enabled if the host controller does not
+	 * support UIC command
+	 */
+	UFSHCD_QUIRK_BROKEN_UIC_CMD			= 1 << 15,
+
+	/*
+	 * This quirk needs to be enabled if the host controller cannot
+	 * support physical host configuration.
+	 */
+	UFSHCD_QUIRK_SKIP_PH_CONFIGURATION		= 1 << 16,
+
+	/*
+	 * This quirk needs to be enabled if the host controller has
+	 * 64-bit addressing supported capability but it doesn't work.
+	 */
+	UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS		= 1 << 17,
+
+	/*
+	 * This quirk needs to be enabled if the host controller has
+	 * auto-hibernate capability but it's FASTAUTO only.
+	 */
+	UFSHCD_QUIRK_HIBERN_FASTAUTO			= 1 << 18,
+
+	/*
+	 * This quirk needs to be enabled if the host controller needs
+	 * to reinit the device after switching to maximum gear.
+	 */
+	UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH       = 1 << 19,
+
+	/*
+	 * Some host raises interrupt (per queue) in addition to
+	 * CQES (traditional) when ESI is disabled.
+	 * Enable this quirk will disable CQES and use per queue interrupt.
+	 */
+	UFSHCD_QUIRK_MCQ_BROKEN_INTR			= 1 << 20,
+
+	/*
+	 * Some host does not implement SQ Run Time Command (SQRTC) register
+	 * thus need this quirk to skip related flow.
+	 */
+	UFSHCD_QUIRK_MCQ_BROKEN_RTC			= 1 << 21,
+
+	/*
+	 * This quirk needs to be enabled if the host controller supports inline
+	 * encryption but it needs to initialize the crypto capabilities in a
+	 * nonstandard way and/or needs to override blk_crypto_ll_ops.  If
+	 * enabled, the standard code won't initialize the blk_crypto_profile;
+	 * ufs_hba_variant_ops::init() must do it instead.
+	 */
+	UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE		= 1 << 22,
+
+	/*
+	 * This quirk needs to be enabled if the host controller supports inline
+	 * encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e.
+	 * host controller initialization fails if that bit is set.
+	 */
+	UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE		= 1 << 23,
+
+	/*
+	 * This quirk needs to be enabled if the host controller driver copies
+	 * cryptographic keys into the PRDT in order to send them to hardware,
+	 * and therefore the PRDT should be zeroized after each request (as per
+	 * the standard best practice for managing keys).
+	 */
+	UFSHCD_QUIRK_KEYS_IN_PRDT			= 1 << 24,
+
+	/*
+	 * This quirk indicates that the controller reports the value 1 (not
+	 * supported) in the Legacy Single DoorBell Support (LSDBS) bit of the
+	 * Controller Capabilities register although it supports the legacy
+	 * single doorbell mode.
+	 */
+	UFSHCD_QUIRK_BROKEN_LSDBS_CAP			= 1 << 25,
+};
 
 	/* Virtual memory reference */
 	struct utp_transfer_cmd_desc *ucdl;