| Message ID | 20240913083724.1217691-1-quic_qianyu@quicinc.com |
|---|---|
| Headers | show |
| Series | Add support for PCIe3 on x1e80100 | expand |
On Fri, Sep 13, 2024 at 01:37:24AM GMT, Qiang Yu wrote: > Describe PCIe3 controller and PHY. Also add required system resources like > regulators, clocks, interrupts and registers configuration for PCIe3. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 202 ++++++++++++++++++++++++- > 1 file changed, 201 insertions(+), 1 deletion(-) I didn't verify the addresses, the rest LGTM Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On Fri, Sep 13, 2024 at 03:30:59PM +0300, Dmitry Baryshkov wrote: > On Fri, Sep 13, 2024 at 01:37:21AM GMT, Qiang Yu wrote: > > Add OPP table so that PCIe is able to adjust power domain performance > > state and ICC peak bw according to PCIe gen speed and link width. > > > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > > --- > > Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > > index a9db0a231563..e2d6719ca54d 100644 > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > > @@ -70,6 +70,10 @@ properties: > > - const: pci # PCIe core reset > > - const: link_down # PCIe link down reset > > > > + operating-points-v2: true > > + opp-table: > > + type: object > > I think these properties are generic enough and we might want to have > them for most if not all platforms. Maybe we should move them to > qcom,pcie-common.yaml? > Agree. It should be moved to qcom,pcie-common.yaml. - Mani > Krzysztof, Mani, WDYT? > > > + > > allOf: > > - $ref: qcom,pcie-common.yaml# > > > > -- > > 2.34.1 > > > > > > -- > > linux-phy mailing list > > linux-phy@lists.infradead.org > > https://lists.infradead.org/mailman/listinfo/linux-phy > > -- > With best wishes > Dmitry
On Fri, Sep 13, 2024 at 01:37:24AM -0700, Qiang Yu wrote: > Describe PCIe3 controller and PHY. Also add required system resources like > regulators, clocks, interrupts and registers configuration for PCIe3. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 202 ++++++++++++++++++++++++- > 1 file changed, 201 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index a36076e3c56b..a7703e4974a6 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -744,7 +744,7 @@ gcc: clock-controller@100000 { > > clocks = <&bi_tcxo_div2>, > <&sleep_clk>, > - <0>, > + <&pcie3_phy>, > <&pcie4_phy>, > <&pcie5_phy>, > <&pcie6a_phy>, > @@ -2907,6 +2907,206 @@ mmss_noc: interconnect@1780000 { > #interconnect-cells = <2>; > }; > > + pcie3: pci@1bd0000 { pcie@ > + device_type = "pci"; > + compatible = "qcom,pcie-x1e80100"; > + reg = <0 0x01bd0000 0 0x3000>, > + <0 0x78000000 0 0xf1d>, 0x0 here and below. > + <0 0x78000f40 0 0xa8>, > + <0 0x78001000 0 0x1000>, > + <0 0x78100000 0 0x100000>, > + <0 0x01bd3000 0 0x1000>; > + reg-names = "parf", > + "dbi", > + "elbi", > + "atu", > + "config", > + "mhi"; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>, > + <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>, > + <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; > + bus-range = <0x00 0xff>; > + > + dma-coherent; > + > + linux,pci-domain = <3>; > + num-lanes = <8>; > + > + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "msi0", > + "msi1", > + "msi2", > + "msi3", > + "msi4", > + "msi5", > + "msi6", > + "msi7"; Can you add 'global' interrupt as well? While doing so, please make sure the global_irq related patches are applied and Link up works fine. Those patches are already in linux-next. > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc 0 0 0 220 IRQ_TYPE_LEVEL_HIGH>, Use GIC_SPI for the parent interrupt specifier. - Mani > + <0 0 0 2 &intc 0 0 0 221 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &intc 0 0 0 237 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &intc 0 0 0 238 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_PCIE_3_AUX_CLK>, > + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_3_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, > + <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, > + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; > + clock-names = "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a", > + "noc_aggr", > + "cnoc_sf_axi"; > + > + assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; > + assigned-clock-rates = <19200000>; > + > + interconnects = <&pcie_south_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "pcie-mem", > + "cpu-pcie"; > + > + resets = <&gcc GCC_PCIE_3_BCR>, > + <&gcc GCC_PCIE_3_LINK_DOWN_BCR>; > + reset-names = "pci", > + "link_down"; > + > + power-domains = <&gcc GCC_PCIE_3_GDSC>; > + > + phys = <&pcie3_phy>; > + phy-names = "pciephy"; > + > + operating-points-v2 = <&pcie3_opp_table>; > + > + status = "disabled"; > + > + pcie3_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + /* GEN 1 x1 */ > + opp-2500000 { > + opp-hz = /bits/ 64 <2500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <250000 1>; > + }; > + > + /* GEN 1 x2 and GEN 2 x1 */ > + opp-5000000 { > + opp-hz = /bits/ 64 <5000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <500000 1>; > + }; > + > + /* GEN 1 x4 and GEN 2 x2 */ > + opp-10000000 { > + opp-hz = /bits/ 64 <10000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <1000000 1>; > + }; > + > + /* GEN 1 x8 and GEN 2 x4 */ > + opp-20000000 { > + opp-hz = /bits/ 64 <20000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <2000000 1>; > + }; > + > + /* GEN 2 x8 */ > + opp-40000000 { > + opp-hz = /bits/ 64 <40000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <4000000 1>; > + }; > + > + /* GEN 3 x1 */ > + opp-8000000 { > + opp-hz = /bits/ 64 <8000000>; > + required-opps = <&rpmhpd_opp_svs>; > + opp-peak-kBps = <984500 1>; > + }; > + > + /* GEN 3 x2 and GEN 4 x1 */ > + opp-16000000 { > + opp-hz = /bits/ 64 <16000000>; > + required-opps = <&rpmhpd_opp_svs>; > + opp-peak-kBps = <1969000 1>; > + }; > + > + /* GEN 3 x4 and GEN 4 x2 */ > + opp-32000000 { > + opp-hz = /bits/ 64 <32000000>; > + required-opps = <&rpmhpd_opp_svs>; > + opp-peak-kBps = <3938000 1>; > + }; > + > + /* GEN 3 x8 and GEN 4 x4 */ > + opp-64000000 { > + opp-hz = /bits/ 64 <64000000>; > + required-opps = <&rpmhpd_opp_svs>; > + opp-peak-kBps = <7876000 1>; > + }; > + > + /* GEN 4 x8 */ > + opp-128000000 { > + opp-hz = /bits/ 64 <128000000>; > + required-opps = <&rpmhpd_opp_svs>; > + opp-peak-kBps = <15753000 1>; > + }; > + }; > + }; > + > + pcie3_phy: phy@1be0000 { > + compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy"; > + reg = <0 0x01be0000 0 0x10000>; > + > + clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, > + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, > + <&tcsr TCSR_PCIE_8L_CLKREF_EN>, > + <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, > + <&gcc GCC_PCIE_3_PIPE_CLK>, > + <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; > + clock-names = "aux", > + "cfg_ahb", > + "ref", > + "rchng", > + "pipe", > + "pipediv2"; > + > + resets = <&gcc GCC_PCIE_3_PHY_BCR>, > + <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; > + reset-names = "phy", > + "phy_nocsr"; > + > + assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; > + assigned-clock-rates = <100000000>; > + > + power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>; > + > + #clock-cells = <0>; > + clock-output-names = "pcie3_pipe_clk"; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > pcie6a: pci@1bf8000 { > device_type = "pci"; > compatible = "qcom,pcie-x1e80100"; > -- > 2.34.1 >
Hi qiang, In next series can you add logic in controller driver to have new ops for this x1e80100 since this hardware has smmuv3 support but currently the ops_1_9_0 ops which is being used has configuring bdf to sid table which will be not present for this devices. - Krishna Chaitanya. On 9/13/2024 2:07 PM, Qiang Yu wrote: > This series add support for PCIe3 on x1e80100. > > PCIe3 needs additional set of clocks, regulators and new set of PCIe QMP > PHY configuration compare other PCIe instances on x1e80100. Hence add > required resource configuration and usage for PCIe3. > > v2->v1: > 1. Squash [PATCH 1/8], [PATCH 2/8],[PATCH 3/8] into one patch and make the > indentation consistent. > 2. Put dts patch at the end of the patchset. > 3. Put dt-binding patch at the first of the patchset. > 4. Add a new patch where opp-table is added in dt-binding to avoid dtbs > checking error. > 5. Remove GCC_PCIE_3_AUX_CLK, RPMH_CXO_CLK, put in TCSR_PCIE_8L_CLKREF_EN > as ref. > 6. Remove lane_broadcasting. > 7. Add 64 bit bar, Remove GCC_PCIE_3_PIPE_CLK_SRC, > GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK is changed to > GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK. > 8. Add Reviewed-by tag. > 9. Remove [PATCH 7/8], [PATCH 8/8]. > > Qiang Yu (5): > dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 > QMP PCIe PHY Gen4 x8 > dt-bindings: PCI: qcom: Add OPP table for X1E80100 > phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 > clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks > arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 > > .../bindings/pci/qcom,pcie-x1e80100.yaml | 4 + > .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 + > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 202 ++++++++++++++++- > drivers/clk/qcom/gcc-x1e80100.c | 10 +- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 211 ++++++++++++++++++ > .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h | 25 +++ > drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h | 19 ++ > 7 files changed, 468 insertions(+), 6 deletions(-) > create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h > create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h >
On Fri, Sep 13, 2024 at 07:06:19PM +0530, Manivannan Sadhasivam wrote: > On Fri, Sep 13, 2024 at 03:30:59PM +0300, Dmitry Baryshkov wrote: > > On Fri, Sep 13, 2024 at 01:37:21AM GMT, Qiang Yu wrote: > > > Add OPP table so that PCIe is able to adjust power domain performance > > > state and ICC peak bw according to PCIe gen speed and link width. > > > > > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > > > --- > > > Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 4 ++++ > > > 1 file changed, 4 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > > > index a9db0a231563..e2d6719ca54d 100644 > > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > > > @@ -70,6 +70,10 @@ properties: > > > - const: pci # PCIe core reset > > > - const: link_down # PCIe link down reset > > > > > > + operating-points-v2: true > > > + opp-table: > > > + type: object > > > > I think these properties are generic enough and we might want to have > > them for most if not all platforms. Maybe we should move them to > > qcom,pcie-common.yaml? > > > > Agree. It should be moved to qcom,pcie-common.yaml. Yep, ack. Best regards, Krzysztof
This series add support for PCIe3 on x1e80100. PCIe3 needs additional set of clocks, regulators and new set of PCIe QMP PHY configuration compare other PCIe instances on x1e80100. Hence add required resource configuration and usage for PCIe3. v2->v1: 1. Squash [PATCH 1/8], [PATCH 2/8],[PATCH 3/8] into one patch and make the indentation consistent. 2. Put dts patch at the end of the patchset. 3. Put dt-binding patch at the first of the patchset. 4. Add a new patch where opp-table is added in dt-binding to avoid dtbs checking error. 5. Remove GCC_PCIE_3_AUX_CLK, RPMH_CXO_CLK, put in TCSR_PCIE_8L_CLKREF_EN as ref. 6. Remove lane_broadcasting. 7. Add 64 bit bar, Remove GCC_PCIE_3_PIPE_CLK_SRC, GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK is changed to GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK. 8. Add Reviewed-by tag. 9. Remove [PATCH 7/8], [PATCH 8/8]. Qiang Yu (5): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 dt-bindings: PCI: qcom: Add OPP table for X1E80100 phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 .../bindings/pci/qcom,pcie-x1e80100.yaml | 4 + .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 + arch/arm64/boot/dts/qcom/x1e80100.dtsi | 202 ++++++++++++++++- drivers/clk/qcom/gcc-x1e80100.c | 10 +- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 211 ++++++++++++++++++ .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h | 25 +++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h | 19 ++ 7 files changed, 468 insertions(+), 6 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h