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[v2,00/29] target/arm: AdvSIMD decodetree conversion, part 4

Message ID 20240909162240.647173-1-richard.henderson@linaro.org
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Series target/arm: AdvSIMD decodetree conversion, part 4 | expand

Message

Richard Henderson Sept. 9, 2024, 4:22 p.m. UTC 
First post-9.1 queue flush.

r~

Richard Henderson (29):
  target/arm: Replace tcg_gen_dupi_vec with constants in gengvec.c
  target/arm: Replace tcg_gen_dupi_vec with constants in translate-sve.c
  target/arm: Use cmpsel in gen_ushl_vec
  target/arm: Use cmpsel in gen_sshl_vec
  target/arm: Use tcg_gen_extract2_i64 for EXT
  target/arm: Convert EXT to decodetree
  target/arm: Convert TBL, TBX to decodetree
  target/arm: Convert UZP, TRN, ZIP to decodetree
  target/arm: Simplify do_reduction_op
  target/arm: Convert ADDV, *ADDLV, *MAXV, *MINV to decodetree
  target/arm: Convert FMAXNMV, FMINNMV, FMAXV, FMINV to decodetree
  target/arm: Convert FMOVI (scalar, immediate) to decodetree
  target/arm: Convert MOVI, FMOV, ORR, BIC (vector immediate) to
    decodetree
  target/arm: Introduce gen_gvec_sshr, gen_gvec_ushr
  target/arm: Fix whitespace near gen_srshr64_i64
  target/arm: Convert handle_vec_simd_shri to decodetree
  target/arm: Convert handle_vec_simd_shli to decodetree
  target/arm: Use {,s}extract in handle_vec_simd_wshli
  target/arm: Convert SSHLL, USHLL to decodetree
  target/arm: Push tcg_rnd into handle_shri_with_rndacc
  target/arm: Split out subroutines of handle_shri_with_rndacc
  target/arm: Convert SHRN, RSHRN to decodetree
  target/arm: Convert handle_scalar_simd_shri to decodetree
  target/arm: Convert handle_scalar_simd_shli to decodetree
  target/arm: Convert VQSHL, VQSHLU to gvec
  target/arm: Widen NeonGenNarrowEnvFn return to 64 bits
  target/arm: Convert SQSHL, UQSHL, SQSHLU (immediate) to decodetree
  target/arm: Convert vector [US]QSHRN, [US]QRSHRN, SQSHRUN to
    decodetree
  target/arm: Convert scalar [US]QSHRN, [US]QRSHRN, SQSHRUN to
    decodetree

 target/arm/helper.h             |   34 +-
 target/arm/tcg/translate.h      |   14 +-
 target/arm/tcg/gengvec.c        |  121 +-
 target/arm/tcg/neon_helper.c    |   55 +-
 target/arm/tcg/translate-a64.c  | 2081 +++++++++++++------------------
 target/arm/tcg/translate-neon.c |  179 +--
 target/arm/tcg/translate-sve.c  |  128 +-
 target/arm/tcg/a64.decode       |  257 ++++
 target/arm/tcg/neon-dp.decode   |    6 +-
 9 files changed, 1377 insertions(+), 1498 deletions(-)

Comments

Peter Maydell Sept. 10, 2024, 3:30 p.m. UTC | #1 
On Mon, 9 Sept 2024 at 17:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> First post-9.1 queue flush.
>
> r~
>
> Richard Henderson (29):
>   target/arm: Replace tcg_gen_dupi_vec with constants in gengvec.c
>   target/arm: Replace tcg_gen_dupi_vec with constants in translate-sve.c
>   target/arm: Use cmpsel in gen_ushl_vec
>   target/arm: Use cmpsel in gen_sshl_vec
>   target/arm: Use tcg_gen_extract2_i64 for EXT
>   target/arm: Convert EXT to decodetree
>   target/arm: Convert TBL, TBX to decodetree
>   target/arm: Convert UZP, TRN, ZIP to decodetree
>   target/arm: Simplify do_reduction_op
>   target/arm: Convert ADDV, *ADDLV, *MAXV, *MINV to decodetree
>   target/arm: Convert FMAXNMV, FMINNMV, FMAXV, FMINV to decodetree
>   target/arm: Convert FMOVI (scalar, immediate) to decodetree
>   target/arm: Convert MOVI, FMOV, ORR, BIC (vector immediate) to
>     decodetree
>   target/arm: Introduce gen_gvec_sshr, gen_gvec_ushr
>   target/arm: Fix whitespace near gen_srshr64_i64
>   target/arm: Convert handle_vec_simd_shri to decodetree
>   target/arm: Convert handle_vec_simd_shli to decodetree
>   target/arm: Use {,s}extract in handle_vec_simd_wshli
>   target/arm: Convert SSHLL, USHLL to decodetree
>   target/arm: Push tcg_rnd into handle_shri_with_rndacc
>   target/arm: Split out subroutines of handle_shri_with_rndacc
>   target/arm: Convert SHRN, RSHRN to decodetree
>   target/arm: Convert handle_scalar_simd_shri to decodetree
>   target/arm: Convert handle_scalar_simd_shli to decodetree
>   target/arm: Convert VQSHL, VQSHLU to gvec
>   target/arm: Widen NeonGenNarrowEnvFn return to 64 bits
>   target/arm: Convert SQSHL, UQSHL, SQSHLU (immediate) to decodetree
>   target/arm: Convert vector [US]QSHRN, [US]QRSHRN, SQSHRUN to
>     decodetree
>   target/arm: Convert scalar [US]QSHRN, [US]QRSHRN, SQSHRUN to
>     decodetree

Other than my comments on the NeonGenNarrowEnvFn patch,
series
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM