| Message ID | a3fde99c2e522ef1fbf4e4bb125bc1d97a715eaf.1724159867.git.andrea.porta@suse.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for RaspberryPi RP1 PCI device using a DT overlay | expand |
Hi Krzysztof, On 10:43 Wed 21 Aug , Krzysztof Kozlowski wrote: > On Tue, Aug 20, 2024 at 04:36:13PM +0200, Andrea della Porta wrote: > > RaspberryPi RP1 is multi function PCI endpoint device that > > exposes several subperipherals via PCI BAR. > > Add an ethernet node for Cadence MACB to the RP1 dtso > > > > Signed-off-by: Andrea della Porta <andrea.porta@suse.com> > > --- > > arch/arm64/boot/dts/broadcom/rp1.dtso | 23 +++++++++++++++++++++++ > > 1 file changed, 23 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/broadcom/rp1.dtso b/arch/arm64/boot/dts/broadcom/rp1.dtso > > index d80178a278ee..b40e203c28d5 100644 > > --- a/arch/arm64/boot/dts/broadcom/rp1.dtso > > +++ b/arch/arm64/boot/dts/broadcom/rp1.dtso > > @@ -78,6 +78,29 @@ rp1_clocks: clocks@c040018000 { > > <50000000>; // RP1_CLK_ETH_TSU > > }; > > > > + rp1_eth: ethernet@c040100000 { > > + reg = <0xc0 0x40100000 0x0 0x4000>; > > + compatible = "cdns,macb"; > > Please start using DTS coding style... Ack. Regards, Andrea > > Best regards, > Krzysztof >
diff --git a/arch/arm64/boot/dts/broadcom/rp1.dtso b/arch/arm64/boot/dts/broadcom/rp1.dtso index d80178a278ee..b40e203c28d5 100644 --- a/arch/arm64/boot/dts/broadcom/rp1.dtso +++ b/arch/arm64/boot/dts/broadcom/rp1.dtso @@ -78,6 +78,29 @@ rp1_clocks: clocks@c040018000 { <50000000>; // RP1_CLK_ETH_TSU }; + rp1_eth: ethernet@c040100000 { + reg = <0xc0 0x40100000 0x0 0x4000>; + compatible = "cdns,macb"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <RP1_INT_ETH IRQ_TYPE_LEVEL_HIGH>; + clocks = <&macb_pclk &macb_hclk &rp1_clocks RP1_CLK_ETH_TSU>; + clock-names = "pclk", "hclk", "tsu_clk"; + phy-mode = "rgmii-id"; + cdns,aw2w-max-pipe = /bits/ 8 <8>; + cdns,ar2r-max-pipe = /bits/ 8 <8>; + cdns,use-aw2b-fill; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&phy1>; + phy-reset-gpios = <&rp1_gpio 32 GPIO_ACTIVE_LOW>; + phy-reset-duration = <5>; + + phy1: ethernet-phy@1 { + reg = <0x1>; + brcm,powerdown-enable; + }; + }; + rp1_gpio: pinctrl@c0400d0000 { reg = <0xc0 0x400d0000 0x0 0xc000>, <0xc0 0x400e0000 0x0 0xc000>,
RaspberryPi RP1 is multi function PCI endpoint device that exposes several subperipherals via PCI BAR. Add an ethernet node for Cadence MACB to the RP1 dtso Signed-off-by: Andrea della Porta <andrea.porta@suse.com> --- arch/arm64/boot/dts/broadcom/rp1.dtso | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)