| Message ID | 20240716150336.2042-7-shiju.jose@huawei.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | EDAC: Scrub: Introduce generic EDAC RAS control feature driver + CXL/ACPI-RAS2 drivers | expand |
On Tue, Jul 16, 2024 at 04:03:30PM +0100, shiju.jose@huawei.com wrote: > From: Shiju Jose <shiju.jose@huawei.com> > > Add support for SET_FEATURE mailbox command. > > CXL spec 3.1 section 8.2.9.6 describes optional device specific features. > CXL devices supports features with changeable attributes. > The settings of a feature can be optionally modified using Set Feature > command. Add more specific spec reference to the command here: 8.2.9.6.3. The same suggestions for get supported features and get feature commands. > > Signed-off-by: Shiju Jose <shiju.jose@huawei.com> > --- > drivers/cxl/core/mbox.c | 71 +++++++++++++++++++++++++++++++++++++++++ > drivers/cxl/cxlmem.h | 33 +++++++++++++++++++ > 2 files changed, 104 insertions(+) > > diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c > index b1eeed508459..50ecd2bd7372 100644 > --- a/drivers/cxl/core/mbox.c > +++ b/drivers/cxl/core/mbox.c > @@ -1388,6 +1388,77 @@ size_t cxl_get_feature(struct cxl_memdev_state *mds, > } > EXPORT_SYMBOL_NS_GPL(cxl_get_feature, CXL); > > +/* > + * FEAT_DATA_MIN_PAYLOAD_SIZE - min extra number of bytes should be > + * available in the mailbox for storing the actual feature data so that > + * the feature data transfer would work as expected. > + */ > +#define FEAT_DATA_MIN_PAYLOAD_SIZE 10 > +int cxl_set_feature(struct cxl_memdev_state *mds, > + const uuid_t feat_uuid, u8 feat_version, > + void *feat_data, size_t feat_data_size, > + u8 feat_flag) > +{ > + struct cxl_memdev_set_feat_pi { > + struct cxl_mbox_set_feat_hdr hdr; > + u8 feat_data[]; > + } __packed; > + size_t data_in_size, data_sent_size = 0; > + struct cxl_mbox_cmd mbox_cmd; > + size_t hdr_size; > + int rc = 0; > + > + struct cxl_memdev_set_feat_pi *pi __free(kfree) = > + kmalloc(mds->payload_size, GFP_KERNEL); > + pi->hdr.uuid = feat_uuid; > + pi->hdr.version = feat_version; > + feat_flag &= ~CXL_SET_FEAT_FLAG_DATA_TRANSFER_MASK; Although we may not support it yet, should we set bit[3] (saved across reset) since we already defined CXL_SET_FEAT_FLAG_DATA_SAVED_ACROSS_RESET and it is not used? Fan > + hdr_size = sizeof(pi->hdr); > + /* > + * Check minimum mbox payload size is available for > + * the feature data transfer. > + */ > + if (hdr_size + FEAT_DATA_MIN_PAYLOAD_SIZE > mds->payload_size) > + return -ENOMEM; > + > + if ((hdr_size + feat_data_size) <= mds->payload_size) { > + pi->hdr.flags = cpu_to_le32(feat_flag | > + CXL_SET_FEAT_FLAG_FULL_DATA_TRANSFER); > + data_in_size = feat_data_size; > + } else { > + pi->hdr.flags = cpu_to_le32(feat_flag | > + CXL_SET_FEAT_FLAG_INITIATE_DATA_TRANSFER); > + data_in_size = mds->payload_size - hdr_size; > + } > + > + do { > + pi->hdr.offset = cpu_to_le16(data_sent_size); > + memcpy(pi->feat_data, feat_data + data_sent_size, data_in_size); > + mbox_cmd = (struct cxl_mbox_cmd) { > + .opcode = CXL_MBOX_OP_SET_FEATURE, > + .size_in = hdr_size + data_in_size, > + .payload_in = pi, > + }; > + rc = cxl_internal_send_cmd(mds, &mbox_cmd); > + if (rc < 0) > + return rc; > + > + data_sent_size += data_in_size; > + if (data_sent_size >= feat_data_size) > + return 0; > + > + if ((feat_data_size - data_sent_size) <= (mds->payload_size - hdr_size)) { > + data_in_size = feat_data_size - data_sent_size; > + pi->hdr.flags = cpu_to_le32(feat_flag | > + CXL_SET_FEAT_FLAG_FINISH_DATA_TRANSFER); > + } else { > + pi->hdr.flags = cpu_to_le32(feat_flag | > + CXL_SET_FEAT_FLAG_CONTINUE_DATA_TRANSFER); > + } > + } while (true); > +} > +EXPORT_SYMBOL_NS_GPL(cxl_set_feature, CXL); > + > int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, > struct cxl_region *cxlr) > { > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h > index 25698a6fbe66..c3cb8e2736b5 100644 > --- a/drivers/cxl/cxlmem.h > +++ b/drivers/cxl/cxlmem.h > @@ -532,6 +532,7 @@ enum cxl_opcode { > CXL_MBOX_OP_GET_SUP_LOG_SUBLIST = 0x0405, > CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500, > CXL_MBOX_OP_GET_FEATURE = 0x0501, > + CXL_MBOX_OP_SET_FEATURE = 0x0502, > CXL_MBOX_OP_IDENTIFY = 0x4000, > CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, > CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, > @@ -780,6 +781,34 @@ struct cxl_mbox_get_feat_in { > u8 selection; > } __packed; > > +/* > + * Set Feature CXL 3.1 Spec 8.2.9.6.3 > + */ > + > +/* > + * Set Feature input payload > + * CXL rev 3.1 section 8.2.9.6.3 Table 8-101 > + */ > +/* Set Feature : Payload in flags */ > +#define CXL_SET_FEAT_FLAG_DATA_TRANSFER_MASK GENMASK(2, 0) > +enum cxl_set_feat_flag_data_transfer { > + CXL_SET_FEAT_FLAG_FULL_DATA_TRANSFER, > + CXL_SET_FEAT_FLAG_INITIATE_DATA_TRANSFER, > + CXL_SET_FEAT_FLAG_CONTINUE_DATA_TRANSFER, > + CXL_SET_FEAT_FLAG_FINISH_DATA_TRANSFER, > + CXL_SET_FEAT_FLAG_ABORT_DATA_TRANSFER, > + CXL_SET_FEAT_FLAG_DATA_TRANSFER_MAX > +}; > +#define CXL_SET_FEAT_FLAG_DATA_SAVED_ACROSS_RESET BIT(3) > + > +struct cxl_mbox_set_feat_hdr { > + uuid_t uuid; > + __le32 flags; > + __le16 offset; > + u8 version; > + u8 rsvd[9]; > +} __packed; > + > /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ > struct cxl_mbox_poison_in { > __le64 offset; > @@ -918,6 +947,10 @@ size_t cxl_get_feature(struct cxl_memdev_state *mds, > const uuid_t feat_uuid, void *feat_out, > size_t feat_out_size, > enum cxl_get_feat_selection selection); > +int cxl_set_feature(struct cxl_memdev_state *mds, > + const uuid_t feat_uuid, u8 feat_version, > + void *feat_data, size_t feat_data_size, > + u8 feat_flag); > int cxl_poison_state_init(struct cxl_memdev_state *mds); > int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, > struct cxl_region *cxlr); > -- > 2.34.1 >
>-----Original Message----- >From: nifan.cxl@gmail.com <nifan.cxl@gmail.com> >Sent: 17 July 2024 21:14 >To: Shiju Jose <shiju.jose@huawei.com> >Cc: linux-edac@vger.kernel.org; linux-cxl@vger.kernel.org; linux- >acpi@vger.kernel.org; linux-mm@kvack.org; linux-kernel@vger.kernel.org; >bp@alien8.de; tony.luck@intel.com; rafael@kernel.org; lenb@kernel.org; >mchehab@kernel.org; dan.j.williams@intel.com; dave@stgolabs.net; Jonathan >Cameron <jonathan.cameron@huawei.com>; dave.jiang@intel.com; >alison.schofield@intel.com; vishal.l.verma@intel.com; ira.weiny@intel.com; >david@redhat.com; Vilas.Sridharan@amd.com; leo.duran@amd.com; >Yazen.Ghannam@amd.com; rientjes@google.com; jiaqiyan@google.com; >Jon.Grimm@amd.com; dave.hansen@linux.intel.com; >naoya.horiguchi@nec.com; james.morse@arm.com; jthoughton@google.com; >somasundaram.a@hpe.com; erdemaktas@google.com; pgonda@google.com; >duenwen@google.com; mike.malvestuto@intel.com; gthelen@google.com; >wschwartz@amperecomputing.com; dferguson@amperecomputing.com; >wbs@os.amperecomputing.com; nifan.cxl@gmail.com; tanxiaofei ><tanxiaofei@huawei.com>; Zengtao (B) <prime.zeng@hisilicon.com>; Roberto >Sassu <roberto.sassu@huawei.com>; kangkang.shen@futurewei.com; >wanghuiqiang <wanghuiqiang@huawei.com>; Linuxarm ><linuxarm@huawei.com> >Subject: Re: [RFC PATCH v9 06/11] cxl/mbox: Add SET_FEATURE mailbox >command > >On Tue, Jul 16, 2024 at 04:03:30PM +0100, shiju.jose@huawei.com wrote: >> From: Shiju Jose <shiju.jose@huawei.com> >> >> Add support for SET_FEATURE mailbox command. >> >> CXL spec 3.1 section 8.2.9.6 describes optional device specific features. >> CXL devices supports features with changeable attributes. >> The settings of a feature can be optionally modified using Set Feature >> command. > >Add more specific spec reference to the command here: 8.2.9.6.3. >The same suggestions for get supported features and get feature commands. Will do. > >> >> Signed-off-by: Shiju Jose <shiju.jose@huawei.com> >> --- >> drivers/cxl/core/mbox.c | 71 >+++++++++++++++++++++++++++++++++++++++++ >> drivers/cxl/cxlmem.h | 33 +++++++++++++++++++ >> 2 files changed, 104 insertions(+) >> >> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index >> b1eeed508459..50ecd2bd7372 100644 >> --- a/drivers/cxl/core/mbox.c >> +++ b/drivers/cxl/core/mbox.c >> @@ -1388,6 +1388,77 @@ size_t cxl_get_feature(struct cxl_memdev_state >> *mds, } EXPORT_SYMBOL_NS_GPL(cxl_get_feature, CXL); >> >> +/* >> + * FEAT_DATA_MIN_PAYLOAD_SIZE - min extra number of bytes should be >> + * available in the mailbox for storing the actual feature data so >> +that >> + * the feature data transfer would work as expected. >> + */ >> +#define FEAT_DATA_MIN_PAYLOAD_SIZE 10 int cxl_set_feature(struct >> +cxl_memdev_state *mds, >> + const uuid_t feat_uuid, u8 feat_version, >> + void *feat_data, size_t feat_data_size, >> + u8 feat_flag) >> +{ >> + struct cxl_memdev_set_feat_pi { >> + struct cxl_mbox_set_feat_hdr hdr; >> + u8 feat_data[]; >> + } __packed; >> + size_t data_in_size, data_sent_size = 0; >> + struct cxl_mbox_cmd mbox_cmd; >> + size_t hdr_size; >> + int rc = 0; >> + >> + struct cxl_memdev_set_feat_pi *pi __free(kfree) = >> + kmalloc(mds->payload_size, >GFP_KERNEL); >> + pi->hdr.uuid = feat_uuid; >> + pi->hdr.version = feat_version; >> + feat_flag &= ~CXL_SET_FEAT_FLAG_DATA_TRANSFER_MASK; > >Although we may not support it yet, should we set bit[3] (saved across reset) >since we already defined CXL_SET_FEAT_FLAG_DATA_SAVED_ACROSS_RESET >and it is not used? Will do. > >Fan >> + hdr_size = sizeof(pi->hdr); >> + /* >> + * Check minimum mbox payload size is available for >> + * the feature data transfer. >> + */ >> + if (hdr_size + FEAT_DATA_MIN_PAYLOAD_SIZE > mds->payload_size) >> + return -ENOMEM; >> + >> + if ((hdr_size + feat_data_size) <= mds->payload_size) { >> + pi->hdr.flags = cpu_to_le32(feat_flag | >> + >CXL_SET_FEAT_FLAG_FULL_DATA_TRANSFER); >> + data_in_size = feat_data_size; >> + } else { >> + pi->hdr.flags = cpu_to_le32(feat_flag | >> + >CXL_SET_FEAT_FLAG_INITIATE_DATA_TRANSFER); >> + data_in_size = mds->payload_size - hdr_size; >> + } >> + >> + do { >> + pi->hdr.offset = cpu_to_le16(data_sent_size); >> + memcpy(pi->feat_data, feat_data + data_sent_size, >data_in_size); >> + mbox_cmd = (struct cxl_mbox_cmd) { >> + .opcode = CXL_MBOX_OP_SET_FEATURE, >> + .size_in = hdr_size + data_in_size, >> + .payload_in = pi, >> + }; >> + rc = cxl_internal_send_cmd(mds, &mbox_cmd); >> + if (rc < 0) >> + return rc; >> + >> + data_sent_size += data_in_size; >> + if (data_sent_size >= feat_data_size) >> + return 0; >> + >> + if ((feat_data_size - data_sent_size) <= (mds->payload_size - >hdr_size)) { >> + data_in_size = feat_data_size - data_sent_size; >> + pi->hdr.flags = cpu_to_le32(feat_flag | >> + >CXL_SET_FEAT_FLAG_FINISH_DATA_TRANSFER); >> + } else { >> + pi->hdr.flags = cpu_to_le32(feat_flag | >> + >CXL_SET_FEAT_FLAG_CONTINUE_DATA_TRANSFER); >> + } >> + } while (true); >> +} >> +EXPORT_SYMBOL_NS_GPL(cxl_set_feature, CXL); >> + >> int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, >> struct cxl_region *cxlr) >> { >> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index >> 25698a6fbe66..c3cb8e2736b5 100644 >> --- a/drivers/cxl/cxlmem.h >> +++ b/drivers/cxl/cxlmem.h >> @@ -532,6 +532,7 @@ enum cxl_opcode { >> CXL_MBOX_OP_GET_SUP_LOG_SUBLIST = 0x0405, >> CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500, >> CXL_MBOX_OP_GET_FEATURE = 0x0501, >> + CXL_MBOX_OP_SET_FEATURE = 0x0502, >> CXL_MBOX_OP_IDENTIFY = 0x4000, >> CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, >> CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, >> @@ -780,6 +781,34 @@ struct cxl_mbox_get_feat_in { >> u8 selection; >> } __packed; >> >> +/* >> + * Set Feature CXL 3.1 Spec 8.2.9.6.3 */ >> + >> +/* >> + * Set Feature input payload >> + * CXL rev 3.1 section 8.2.9.6.3 Table 8-101 */ >> +/* Set Feature : Payload in flags */ >> +#define CXL_SET_FEAT_FLAG_DATA_TRANSFER_MASK GENMASK(2, 0) >> +enum cxl_set_feat_flag_data_transfer { >> + CXL_SET_FEAT_FLAG_FULL_DATA_TRANSFER, >> + CXL_SET_FEAT_FLAG_INITIATE_DATA_TRANSFER, >> + CXL_SET_FEAT_FLAG_CONTINUE_DATA_TRANSFER, >> + CXL_SET_FEAT_FLAG_FINISH_DATA_TRANSFER, >> + CXL_SET_FEAT_FLAG_ABORT_DATA_TRANSFER, >> + CXL_SET_FEAT_FLAG_DATA_TRANSFER_MAX >> +}; >> +#define CXL_SET_FEAT_FLAG_DATA_SAVED_ACROSS_RESET BIT(3) >> + >> +struct cxl_mbox_set_feat_hdr { >> + uuid_t uuid; >> + __le32 flags; >> + __le16 offset; >> + u8 version; >> + u8 rsvd[9]; >> +} __packed; >> + >> /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ struct >> cxl_mbox_poison_in { >> __le64 offset; >> @@ -918,6 +947,10 @@ size_t cxl_get_feature(struct cxl_memdev_state >*mds, >> const uuid_t feat_uuid, void *feat_out, >> size_t feat_out_size, >> enum cxl_get_feat_selection selection); >> +int cxl_set_feature(struct cxl_memdev_state *mds, >> + const uuid_t feat_uuid, u8 feat_version, >> + void *feat_data, size_t feat_data_size, >> + u8 feat_flag); >> int cxl_poison_state_init(struct cxl_memdev_state *mds); int >> cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, >> struct cxl_region *cxlr); >> -- >> 2.34.1 >> Thanks, Shiju
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index b1eeed508459..50ecd2bd7372 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -1388,6 +1388,77 @@ size_t cxl_get_feature(struct cxl_memdev_state *mds, } EXPORT_SYMBOL_NS_GPL(cxl_get_feature, CXL); +/* + * FEAT_DATA_MIN_PAYLOAD_SIZE - min extra number of bytes should be + * available in the mailbox for storing the actual feature data so that + * the feature data transfer would work as expected. + */ +#define FEAT_DATA_MIN_PAYLOAD_SIZE 10 +int cxl_set_feature(struct cxl_memdev_state *mds, + const uuid_t feat_uuid, u8 feat_version, + void *feat_data, size_t feat_data_size, + u8 feat_flag) +{ + struct cxl_memdev_set_feat_pi { + struct cxl_mbox_set_feat_hdr hdr; + u8 feat_data[]; + } __packed; + size_t data_in_size, data_sent_size = 0; + struct cxl_mbox_cmd mbox_cmd; + size_t hdr_size; + int rc = 0; + + struct cxl_memdev_set_feat_pi *pi __free(kfree) = + kmalloc(mds->payload_size, GFP_KERNEL); + pi->hdr.uuid = feat_uuid; + pi->hdr.version = feat_version; + feat_flag &= ~CXL_SET_FEAT_FLAG_DATA_TRANSFER_MASK; + hdr_size = sizeof(pi->hdr); + /* + * Check minimum mbox payload size is available for + * the feature data transfer. + */ + if (hdr_size + FEAT_DATA_MIN_PAYLOAD_SIZE > mds->payload_size) + return -ENOMEM; + + if ((hdr_size + feat_data_size) <= mds->payload_size) { + pi->hdr.flags = cpu_to_le32(feat_flag | + CXL_SET_FEAT_FLAG_FULL_DATA_TRANSFER); + data_in_size = feat_data_size; + } else { + pi->hdr.flags = cpu_to_le32(feat_flag | + CXL_SET_FEAT_FLAG_INITIATE_DATA_TRANSFER); + data_in_size = mds->payload_size - hdr_size; + } + + do { + pi->hdr.offset = cpu_to_le16(data_sent_size); + memcpy(pi->feat_data, feat_data + data_sent_size, data_in_size); + mbox_cmd = (struct cxl_mbox_cmd) { + .opcode = CXL_MBOX_OP_SET_FEATURE, + .size_in = hdr_size + data_in_size, + .payload_in = pi, + }; + rc = cxl_internal_send_cmd(mds, &mbox_cmd); + if (rc < 0) + return rc; + + data_sent_size += data_in_size; + if (data_sent_size >= feat_data_size) + return 0; + + if ((feat_data_size - data_sent_size) <= (mds->payload_size - hdr_size)) { + data_in_size = feat_data_size - data_sent_size; + pi->hdr.flags = cpu_to_le32(feat_flag | + CXL_SET_FEAT_FLAG_FINISH_DATA_TRANSFER); + } else { + pi->hdr.flags = cpu_to_le32(feat_flag | + CXL_SET_FEAT_FLAG_CONTINUE_DATA_TRANSFER); + } + } while (true); +} +EXPORT_SYMBOL_NS_GPL(cxl_set_feature, CXL); + int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, struct cxl_region *cxlr) { diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 25698a6fbe66..c3cb8e2736b5 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -532,6 +532,7 @@ enum cxl_opcode { CXL_MBOX_OP_GET_SUP_LOG_SUBLIST = 0x0405, CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500, CXL_MBOX_OP_GET_FEATURE = 0x0501, + CXL_MBOX_OP_SET_FEATURE = 0x0502, CXL_MBOX_OP_IDENTIFY = 0x4000, CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, @@ -780,6 +781,34 @@ struct cxl_mbox_get_feat_in { u8 selection; } __packed; +/* + * Set Feature CXL 3.1 Spec 8.2.9.6.3 + */ + +/* + * Set Feature input payload + * CXL rev 3.1 section 8.2.9.6.3 Table 8-101 + */ +/* Set Feature : Payload in flags */ +#define CXL_SET_FEAT_FLAG_DATA_TRANSFER_MASK GENMASK(2, 0) +enum cxl_set_feat_flag_data_transfer { + CXL_SET_FEAT_FLAG_FULL_DATA_TRANSFER, + CXL_SET_FEAT_FLAG_INITIATE_DATA_TRANSFER, + CXL_SET_FEAT_FLAG_CONTINUE_DATA_TRANSFER, + CXL_SET_FEAT_FLAG_FINISH_DATA_TRANSFER, + CXL_SET_FEAT_FLAG_ABORT_DATA_TRANSFER, + CXL_SET_FEAT_FLAG_DATA_TRANSFER_MAX +}; +#define CXL_SET_FEAT_FLAG_DATA_SAVED_ACROSS_RESET BIT(3) + +struct cxl_mbox_set_feat_hdr { + uuid_t uuid; + __le32 flags; + __le16 offset; + u8 version; + u8 rsvd[9]; +} __packed; + /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ struct cxl_mbox_poison_in { __le64 offset; @@ -918,6 +947,10 @@ size_t cxl_get_feature(struct cxl_memdev_state *mds, const uuid_t feat_uuid, void *feat_out, size_t feat_out_size, enum cxl_get_feat_selection selection); +int cxl_set_feature(struct cxl_memdev_state *mds, + const uuid_t feat_uuid, u8 feat_version, + void *feat_data, size_t feat_data_size, + u8 feat_flag); int cxl_poison_state_init(struct cxl_memdev_state *mds); int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, struct cxl_region *cxlr);