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Wed, 03 Jul 2024 02:59:35 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 4632xYXk013518 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 Jul 2024 02:59:34 GMT Received: from tengfan-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 2 Jul 2024 19:59:11 -0700 From: Tengfei Fan <quic_tengfan@quicinc.com> To: <andersson@kernel.org>, <konrad.dybcio@linaro.org>, <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>, <djakov@kernel.org>, <mturquette@baylibre.com>, <sboyd@kernel.org>, <jassisinghbrar@gmail.com>, <herbert@gondor.apana.org.au>, <davem@davemloft.net>, <manivannan.sadhasivam@linaro.org>, <will@kernel.org>, <joro@8bytes.org>, <conor@kernel.org>, <tglx@linutronix.de>, <amitk@kernel.org>, <thara.gopinath@gmail.com>, <linus.walleij@linaro.org>, <wim@linux-watchdog.org>, <linux@roeck-us.net>, <rafael@kernel.org>, <viresh.kumar@linaro.org>, <vkoul@kernel.org>, <edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>, <mcoquelin.stm32@gmail.com> CC: <robimarko@gmail.com>, <quic_gurus@quicinc.com>, <bartosz.golaszewski@linaro.org>, <kishon@kernel.org>, <quic_wcheng@quicinc.com>, <alim.akhtar@samsung.com>, <avri.altman@wdc.com>, <bvanassche@acm.org>, <agross@kernel.org>, <gregkh@linuxfoundation.org>, <quic_tdas@quicinc.com>, <robin.murphy@arm.com>, <daniel.lezcano@linaro.org>, <rui.zhang@intel.com>, <lukasz.luba@arm.com>, <quic_rjendra@quicinc.com>, <ulf.hansson@linaro.org>, <quic_sibis@quicinc.com>, <otto.pflueger@abscue.de>, <quic_rohiagar@quicinc.com>, <luca@z3ntu.xyz>, <neil.armstrong@linaro.org>, <abel.vesa@linaro.org>, <bhupesh.sharma@linaro.org>, <alexandre.torgue@foss.st.com>, <peppe.cavallaro@st.com>, <joabreu@synopsys.com>, <netdev@vger.kernel.org>, <lpieralisi@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>, <ahalaney@redhat.com>, <krzysztof.kozlowski@linaro.org>, <u.kleine-koenig@pengutronix.de>, <dmitry.baryshkov@linaro.org>, <quic_cang@quicinc.com>, <danila@jiaxyga.com>, <quic_nitirawa@quicinc.com>, <mantas@8devices.com>, <athierry@redhat.com>, <quic_kbajaj@quicinc.com>, <quic_bjorande@quicinc.com>, <quic_msarkar@quicinc.com>, <quic_devipriy@quicinc.com>, <quic_tsoni@quicinc.com>, <quic_rgottimu@quicinc.com>, <quic_shashim@quicinc.com>, <quic_kaushalk@quicinc.com>, <quic_tingweiz@quicinc.com>, <quic_aiquny@quicinc.com>, <srinivas.kandagatla@linaro.org>, <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-pm@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-phy@lists.infradead.org>, <linux-crypto@vger.kernel.org>, <linux-scsi@vger.kernel.org>, <linux-usb@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>, <linux-riscv@lists.infradead.org>, <linux-gpio@vger.kernel.org>, <linux-watchdog@vger.kernel.org>, <linux-pci@vger.kernel.org>, <linux-stm32@st-md-mailman.stormreply.com>, <kernel@quicinc.com>, Tengfei Fan <quic_tengfan@quicinc.com> Subject: [PATCH 00/47] arm64: qcom: dts: add QCS9100 support Date: Wed, 3 Jul 2024 10:58:03 +0800 Message-ID: <20240703025850.2172008-1-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: <linux-usb.vger.kernel.org> List-Subscribe: <mailto:linux-usb+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-usb+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; 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arm64: qcom: dts: add QCS9100 support
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On 7/3/2024 2:28 PM, Conor Dooley wrote: > On Wed, Jul 03, 2024 at 06:45:00AM +0200, Krzysztof Kozlowski wrote: >> On 03/07/2024 05:56, Tengfei Fan wrote: >>> Introduce support for the QCS9100 SoC device tree (DTSI) and the >>> QCS9100 RIDE board DTS. The QCS9100 is a variant of the SA8775p. >>> While the QCS9100 platform is still in the early design stage, the >>> QCS9100 RIDE board is identical to the SA8775p RIDE board, except it >>> mounts the QCS9100 SoC instead of the SA8775p SoC. >> >> The same huge patchset, to huge number of recipients was sent twice. >> First, sorry, this is way too big. Second, it has way too many >> recipients, but this is partially a result of first point. Only >> partially because you put here dozen of totally unrelated emails. Sorry, >> that does not make even sense. See form letter at the end how this >> works. Third, sending it to everyone twice is a way to annoy them off >> twice... Fourth, >> >> Please split your work and do not cc dozen of unrelated folks. > > One of the extra recipients is cos that of that patch I sent adding the > cache bindings to the cache entry, forgetting that that would CC the > riscv list on all cache bindings. I modified that patch to drop the riscv > list from the entry. > > Cheers, > Conor. Thank you, Conor!