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[0/3] util: Add cpuinfo support for riscv

Message ID 20240627180350.128575-1-richard.henderson@linaro.org
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Series util: Add cpuinfo support for riscv | expand

Message

Richard Henderson June 27, 2024, 6:03 p.m. UTC 
Do cpu feature detection in util, like other hosts.
Support the OpenBSD ucontext_t.
Support the Linux __riscv_hwprobe syscall.

r~

Richard Henderson (3):
  util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
  util/cpuinfo-riscv: Support OpenBSD signal frame
  util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall

 meson.build                       |   6 ++
 host/include/riscv/host/cpuinfo.h |  23 ++++++
 tcg/riscv/tcg-target.h            |  46 ++++++------
 util/cpuinfo-riscv.c              | 118 ++++++++++++++++++++++++++++++
 tcg/riscv/tcg-target.c.inc        |  84 ++-------------------
 util/meson.build                  |   2 +
 6 files changed, 178 insertions(+), 101 deletions(-)
 create mode 100644 host/include/riscv/host/cpuinfo.h
 create mode 100644 util/cpuinfo-riscv.c

Comments

Richard Henderson July 2, 2024, 4:26 p.m. UTC | #1 
Ping, particularly from the riscv folk.
I'm keen to get on Brad's *BSD patches in my next PR.

r~

On 6/27/24 11:03, Richard Henderson wrote:
> Do cpu feature detection in util, like other hosts.
> Support the OpenBSD ucontext_t.
> Support the Linux __riscv_hwprobe syscall.
> 
> r~
> 
> Richard Henderson (3):
>    util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
>    util/cpuinfo-riscv: Support OpenBSD signal frame
>    util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall
> 
>   meson.build                       |   6 ++
>   host/include/riscv/host/cpuinfo.h |  23 ++++++
>   tcg/riscv/tcg-target.h            |  46 ++++++------
>   util/cpuinfo-riscv.c              | 118 ++++++++++++++++++++++++++++++
>   tcg/riscv/tcg-target.c.inc        |  84 ++-------------------
>   util/meson.build                  |   2 +
>   6 files changed, 178 insertions(+), 101 deletions(-)
>   create mode 100644 host/include/riscv/host/cpuinfo.h
>   create mode 100644 util/cpuinfo-riscv.c
>