| Message ID | 20240413152013.22307-1-quic_jkona@quicinc.com |
|---|---|
| Headers | show |
| Series | PM: domains: Add control for switching back and forth to HW control | expand |
On 4/14/2024 6:09 PM, Bryan O'Donoghue wrote: > On 13/04/2024 16:20, Jagadeesh Kona wrote: >> The Venus driver requires vcodec GDSC to be ON in SW mode for clock >> operations and move it back to HW mode to gain power benefits. Earlier, >> as there is no interface to switch the GDSC mode from GenPD framework, >> the GDSC is moved to HW control mode as part of GDSC enable callback and >> venus driver is writing to its POWER_CONTROL register to keep the GDSC ON >> from SW whereever required. But the POWER_CONTROL register addresses >> are not constant and can vary across the variants. >> >> Also as per the HW recommendation, the GDSC mode switching needs to be >> controlled from respective GDSC register and this is a uniform approach >> across all the targets. Hence use dev_pm_genpd_set_hwmode() API which >> controls GDSC mode switching using its respective GDSC register. >> >> In venus V6 variants, the vcodec gdsc gets enabled in SW mode by default >> with new HW_CTRL_TRIGGER flag and there is no need to switch it to SW >> mode again after enable, hence add check to avoid switching gdsc to SW >> mode >> again after gdsc enable. Similarly add check to avoid switching GDSC >> to HW >> mode before disabling the GDSC, so GDSC gets enabled in SW mode in the >> next >> enable. >> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >> --- > > When I tested this out on sm8250 a few months ago it was broken. > > I don't quite see in your commit logs, how the breakage was addressed. > > Can you provide some details ? > Thanks Bryan for your review! In earlier series, venus driver is switching the vcodec GDSC to HW control mode before disabling the GDSC by invoking vcodec_control_v4(..., false) in poweroff_coreid(). Due to this, the subsequent GDSC enable from venus driver is failing while polling for GDSC power ON status, since GDSC is under HW control mode and HW can keep the GDSC in disabled state. Now a check is added in poweroff_coreid() to avoid switching the GDSC to HW control mode before disabling the GDSC for Venus V6 variants that use this new API. Hence during the next GDSC enable, GDSC will be in SW mode and GDSC will powerup properly. Thanks, Jagadeesh > --- > bod >
On 13/04/2024 16:20, Jagadeesh Kona wrote: > Some GDSC client drivers require the GDSC mode to be switched dynamically > to HW mode at runtime to gain the power benefits. Typically such client > drivers require the GDSC to be brought up in SW mode initially to enable > the required dependent clocks and configure the hardware to proper state. > Once initial hardware set up is done, they switch the GDSC to HW mode to > save power. At the end of usecase, they switch the GDSC back to SW mode > and disable the GDSC. > > Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and > get_hwmode_dev callbacks for GDSC's whose respective client drivers > require the GDSC mode to be switched dynamically at runtime using > dev_pm_genpd_set_hwmode() API. > > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > drivers/clk/qcom/gdsc.c | 37 +++++++++++++++++++++++++++++++++++++ > drivers/clk/qcom/gdsc.h | 1 + > 2 files changed, 38 insertions(+) > > diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c > index df9618ab7eea..c5f6be8181d8 100644 > --- a/drivers/clk/qcom/gdsc.c > +++ b/drivers/clk/qcom/gdsc.c > @@ -363,6 +363,39 @@ static int gdsc_disable(struct generic_pm_domain *domain) > return 0; > } > > +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct device *dev, bool mode) > +{ > + struct gdsc *sc = domain_to_gdsc(domain); > + int ret; > + > + ret = gdsc_hwctrl(sc, mode); > + if (ret) > + return ret; > + > + /* Wait for 1usec for mode transition to properly complete */ > + udelay(1); A delay I suspect you don't need - if the HW spec says "takes 1 usec for this to take effect" that's 1 usec from io write completion from APSS to another system agent. You poll for the state transition down below anyway. I'd be pretty certain that's a redundant delay. > + > + /* > + * When GDSC is switched to HW mode, HW can disable the GDSC. > + * When GDSC is switched back to SW mode, the GDSC will be enabled > + * again, hence need to poll for GDSC to complete the power up. > + */ > + if (!mode) > + return gdsc_poll_status(sc, GDSC_ON); > + > + return 0; > +} Other than that, seems fine. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
On 14/04/2024 15:52, Jagadeesh Kona wrote: > > > On 4/14/2024 6:09 PM, Bryan O'Donoghue wrote: >> On 13/04/2024 16:20, Jagadeesh Kona wrote: >>> The Venus driver requires vcodec GDSC to be ON in SW mode for clock >>> operations and move it back to HW mode to gain power benefits. Earlier, >>> as there is no interface to switch the GDSC mode from GenPD framework, >>> the GDSC is moved to HW control mode as part of GDSC enable callback and >>> venus driver is writing to its POWER_CONTROL register to keep the >>> GDSC ON >>> from SW whereever required. But the POWER_CONTROL register addresses >>> are not constant and can vary across the variants. >>> >>> Also as per the HW recommendation, the GDSC mode switching needs to be >>> controlled from respective GDSC register and this is a uniform approach >>> across all the targets. Hence use dev_pm_genpd_set_hwmode() API which >>> controls GDSC mode switching using its respective GDSC register. >>> >>> In venus V6 variants, the vcodec gdsc gets enabled in SW mode by default >>> with new HW_CTRL_TRIGGER flag and there is no need to switch it to SW >>> mode again after enable, hence add check to avoid switching gdsc to >>> SW mode >>> again after gdsc enable. Similarly add check to avoid switching GDSC >>> to HW >>> mode before disabling the GDSC, so GDSC gets enabled in SW mode in >>> the next >>> enable. >>> >>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>> --- >> >> When I tested this out on sm8250 a few months ago it was broken. >> >> I don't quite see in your commit logs, how the breakage was addressed. >> >> Can you provide some details ? >> > > Thanks Bryan for your review! > > In earlier series, venus driver is switching the vcodec GDSC to HW > control mode before disabling the GDSC by invoking > vcodec_control_v4(..., false) in poweroff_coreid(). Due to this, the > subsequent GDSC enable from venus driver is failing while polling for > GDSC power ON status, since GDSC is under HW control mode and HW can > keep the GDSC in disabled state. > > Now a check is added in poweroff_coreid() to avoid switching the GDSC to > HW control mode before disabling the GDSC for Venus V6 variants that use > this new API. Hence during the next GDSC enable, GDSC will be in SW mode > and GDSC will powerup properly. Right so the intention is to have HW GDSC control during playback only - and then revert to SW control when no stream is active, right ? I tried your series on today's -next. Here is -next without your changes https://drive.google.com/file/d/1PFuLOlEp582rBQUvuwc9PNZUBxn1ioYf/view?usp=sharing and here is -next with your changes https://drive.google.com/file/d/1PHR4rZnWUH9Wp2B-itT5yCUXIMOMZrwM/view?usp=sharing The first time I tried that test the stopping/stuttering was worse. So yes the original crash was fixed but, this looks like a performance regression to me. Here's the tree I tested with. https://git.codelinaro.org/bryan.odonoghue/kernel/-/tree/linux-next-24-05-23-review?ref_type=heads --- bod
On 4/24/2024 5:46 AM, Bryan O'Donoghue wrote: > On 14/04/2024 15:52, Jagadeesh Kona wrote: >> >> >> On 4/14/2024 6:09 PM, Bryan O'Donoghue wrote: >>> On 13/04/2024 16:20, Jagadeesh Kona wrote: >>>> The Venus driver requires vcodec GDSC to be ON in SW mode for clock >>>> operations and move it back to HW mode to gain power benefits. Earlier, >>>> as there is no interface to switch the GDSC mode from GenPD framework, >>>> the GDSC is moved to HW control mode as part of GDSC enable callback >>>> and >>>> venus driver is writing to its POWER_CONTROL register to keep the >>>> GDSC ON >>>> from SW whereever required. But the POWER_CONTROL register addresses >>>> are not constant and can vary across the variants. >>>> >>>> Also as per the HW recommendation, the GDSC mode switching needs to be >>>> controlled from respective GDSC register and this is a uniform approach >>>> across all the targets. Hence use dev_pm_genpd_set_hwmode() API which >>>> controls GDSC mode switching using its respective GDSC register. >>>> >>>> In venus V6 variants, the vcodec gdsc gets enabled in SW mode by >>>> default >>>> with new HW_CTRL_TRIGGER flag and there is no need to switch it to SW >>>> mode again after enable, hence add check to avoid switching gdsc to >>>> SW mode >>>> again after gdsc enable. Similarly add check to avoid switching GDSC >>>> to HW >>>> mode before disabling the GDSC, so GDSC gets enabled in SW mode in >>>> the next >>>> enable. >>>> >>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>>> --- >>> >>> When I tested this out on sm8250 a few months ago it was broken. >>> >>> I don't quite see in your commit logs, how the breakage was addressed. >>> >>> Can you provide some details ? >>> >> >> Thanks Bryan for your review! >> >> In earlier series, venus driver is switching the vcodec GDSC to HW >> control mode before disabling the GDSC by invoking >> vcodec_control_v4(..., false) in poweroff_coreid(). Due to this, the >> subsequent GDSC enable from venus driver is failing while polling for >> GDSC power ON status, since GDSC is under HW control mode and HW can >> keep the GDSC in disabled state. >> >> Now a check is added in poweroff_coreid() to avoid switching the GDSC >> to HW control mode before disabling the GDSC for Venus V6 variants >> that use this new API. Hence during the next GDSC enable, GDSC will be >> in SW mode and GDSC will powerup properly. > > Right so the intention is to have HW GDSC control during playback only - > and then revert to SW control when no stream is active, right ? > > I tried your series on today's -next. > > Here is -next without your changes > > https://drive.google.com/file/d/1PFuLOlEp582rBQUvuwc9PNZUBxn1ioYf/view?usp=sharing > > and here is -next with your changes > > https://drive.google.com/file/d/1PHR4rZnWUH9Wp2B-itT5yCUXIMOMZrwM/view?usp=sharing > > The first time I tried that test the stopping/stuttering was worse. > > So yes the original crash was fixed but, this looks like a performance > regression to me. > Thanks Bryan for testing this series. Can you please confirm if this issue is observed in every run or only seen during the first run? Also please let me know on which platform this issue is observed? Thanks, Jagadeesh > Here's the tree I tested with. > > https://git.codelinaro.org/bryan.odonoghue/kernel/-/tree/linux-next-24-05-23-review?ref_type=heads > > --- > bod >
On 4/24/2024 5:18 AM, Bryan O'Donoghue wrote: > On 13/04/2024 16:20, Jagadeesh Kona wrote: >> Some GDSC client drivers require the GDSC mode to be switched dynamically >> to HW mode at runtime to gain the power benefits. Typically such client >> drivers require the GDSC to be brought up in SW mode initially to enable >> the required dependent clocks and configure the hardware to proper state. >> Once initial hardware set up is done, they switch the GDSC to HW mode to >> save power. At the end of usecase, they switch the GDSC back to SW mode >> and disable the GDSC. >> >> Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and >> get_hwmode_dev callbacks for GDSC's whose respective client drivers >> require the GDSC mode to be switched dynamically at runtime using >> dev_pm_genpd_set_hwmode() API. >> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >> --- >> drivers/clk/qcom/gdsc.c | 37 +++++++++++++++++++++++++++++++++++++ >> drivers/clk/qcom/gdsc.h | 1 + >> 2 files changed, 38 insertions(+) >> >> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c >> index df9618ab7eea..c5f6be8181d8 100644 >> --- a/drivers/clk/qcom/gdsc.c >> +++ b/drivers/clk/qcom/gdsc.c >> @@ -363,6 +363,39 @@ static int gdsc_disable(struct generic_pm_domain >> *domain) >> return 0; >> } >> +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct >> device *dev, bool mode) >> +{ >> + struct gdsc *sc = domain_to_gdsc(domain); >> + int ret; >> + >> + ret = gdsc_hwctrl(sc, mode); >> + if (ret) >> + return ret; >> + >> + /* Wait for 1usec for mode transition to properly complete */ >> + udelay(1); > > A delay I suspect you don't need - if the HW spec says "takes 1 usec for > this to take effect" that's 1 usec from io write completion from APSS to > another system agent. > > You poll for the state transition down below anyway. > > I'd be pretty certain that's a redundant delay. > Thanks Bryan for your review! This 1usec delay is needed every time GDSC is moved in and out of HW control mode and the reason for same is explained in one of the older gdsc driver change at below link https://lore.kernel.org/all/1484027679-18397-1-git-send-email-rnayak@codeaurora.org/ Thanks, Jagadeesh >> + >> + /* >> + * When GDSC is switched to HW mode, HW can disable the GDSC. >> + * When GDSC is switched back to SW mode, the GDSC will be enabled >> + * again, hence need to poll for GDSC to complete the power up. >> + */ >> + if (!mode) >> + return gdsc_poll_status(sc, GDSC_ON); >> + >> + return 0; >> +} > > Other than that, seems fine. > > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> >
On 24/04/2024 10:45, Jagadeesh Kona wrote: > > Thanks Bryan for testing this series. Can you please confirm if this > issue is observed in every run or only seen during the first run? Also > please let me know on which platform this issue is observed? > > Thanks, > Jagadeesh rb5/sm8250 My observation was on a previous _boot_ the stuttering was worse. There is in the video capture three times that I count where the video halts briefly, I guess we need to vote or set an OPP so the firmware knows not to power-collapse quite so aggressively. --- bod
On 24/04/2024 10:47, Jagadeesh Kona wrote: > > > On 4/24/2024 5:18 AM, Bryan O'Donoghue wrote: >> On 13/04/2024 16:20, Jagadeesh Kona wrote: >>> Some GDSC client drivers require the GDSC mode to be switched >>> dynamically >>> to HW mode at runtime to gain the power benefits. Typically such client >>> drivers require the GDSC to be brought up in SW mode initially to enable >>> the required dependent clocks and configure the hardware to proper >>> state. >>> Once initial hardware set up is done, they switch the GDSC to HW mode to >>> save power. At the end of usecase, they switch the GDSC back to SW mode >>> and disable the GDSC. >>> >>> Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and >>> get_hwmode_dev callbacks for GDSC's whose respective client drivers >>> require the GDSC mode to be switched dynamically at runtime using >>> dev_pm_genpd_set_hwmode() API. >>> >>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>> --- >>> drivers/clk/qcom/gdsc.c | 37 +++++++++++++++++++++++++++++++++++++ >>> drivers/clk/qcom/gdsc.h | 1 + >>> 2 files changed, 38 insertions(+) >>> >>> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c >>> index df9618ab7eea..c5f6be8181d8 100644 >>> --- a/drivers/clk/qcom/gdsc.c >>> +++ b/drivers/clk/qcom/gdsc.c >>> @@ -363,6 +363,39 @@ static int gdsc_disable(struct generic_pm_domain >>> *domain) >>> return 0; >>> } >>> +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct >>> device *dev, bool mode) >>> +{ >>> + struct gdsc *sc = domain_to_gdsc(domain); >>> + int ret; >>> + >>> + ret = gdsc_hwctrl(sc, mode); >>> + if (ret) >>> + return ret; >>> + >>> + /* Wait for 1usec for mode transition to properly complete */ >>> + udelay(1); >> >> A delay I suspect you don't need - if the HW spec says "takes 1 usec >> for this to take effect" that's 1 usec from io write completion from >> APSS to another system agent. >> >> You poll for the state transition down below anyway. >> >> I'd be pretty certain that's a redundant delay. >> > > Thanks Bryan for your review! > > This 1usec delay is needed every time GDSC is moved in and out of HW > control mode and the reason for same is explained in one of the older > gdsc driver change at below link > > https://lore.kernel.org/all/1484027679-18397-1-git-send-email-rnayak@codeaurora.org/ > Right. If that is your precedent then you seem to be missing the mb(); between gdsc_hwctrl(); /* mb(); here */ and this udelay(1); --- bod
On 4/24/2024 3:25 PM, Bryan O'Donoghue wrote: > On 24/04/2024 10:47, Jagadeesh Kona wrote: >> >> >> On 4/24/2024 5:18 AM, Bryan O'Donoghue wrote: >>> On 13/04/2024 16:20, Jagadeesh Kona wrote: >>>> Some GDSC client drivers require the GDSC mode to be switched >>>> dynamically >>>> to HW mode at runtime to gain the power benefits. Typically such client >>>> drivers require the GDSC to be brought up in SW mode initially to >>>> enable >>>> the required dependent clocks and configure the hardware to proper >>>> state. >>>> Once initial hardware set up is done, they switch the GDSC to HW >>>> mode to >>>> save power. At the end of usecase, they switch the GDSC back to SW mode >>>> and disable the GDSC. >>>> >>>> Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and >>>> get_hwmode_dev callbacks for GDSC's whose respective client drivers >>>> require the GDSC mode to be switched dynamically at runtime using >>>> dev_pm_genpd_set_hwmode() API. >>>> >>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>>> --- >>>> drivers/clk/qcom/gdsc.c | 37 +++++++++++++++++++++++++++++++++++++ >>>> drivers/clk/qcom/gdsc.h | 1 + >>>> 2 files changed, 38 insertions(+) >>>> >>>> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c >>>> index df9618ab7eea..c5f6be8181d8 100644 >>>> --- a/drivers/clk/qcom/gdsc.c >>>> +++ b/drivers/clk/qcom/gdsc.c >>>> @@ -363,6 +363,39 @@ static int gdsc_disable(struct >>>> generic_pm_domain *domain) >>>> return 0; >>>> } >>>> +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct >>>> device *dev, bool mode) >>>> +{ >>>> + struct gdsc *sc = domain_to_gdsc(domain); >>>> + int ret; >>>> + >>>> + ret = gdsc_hwctrl(sc, mode); >>>> + if (ret) >>>> + return ret; >>>> + >>>> + /* Wait for 1usec for mode transition to properly complete */ >>>> + udelay(1); >>> >>> A delay I suspect you don't need - if the HW spec says "takes 1 usec >>> for this to take effect" that's 1 usec from io write completion from >>> APSS to another system agent. >>> >>> You poll for the state transition down below anyway. >>> >>> I'd be pretty certain that's a redundant delay. >>> >> >> Thanks Bryan for your review! >> >> This 1usec delay is needed every time GDSC is moved in and out of HW >> control mode and the reason for same is explained in one of the older >> gdsc driver change at below link >> >> https://lore.kernel.org/all/1484027679-18397-1-git-send-email-rnayak@codeaurora.org/ >> > > Right. > > If that is your precedent then you seem to be missing the mb(); between > > gdsc_hwctrl(); > > /* mb(); here */ > > and this > > udelay(1); > Sorry, earlier I shared the link to base patch series which has mb() used, but in the mainlined series of the same patch mb() is removed as per the review comments. Please find the mainlined series link:- https://lore.kernel.org/all/1485145581-517-1-git-send-email-rnayak@codeaurora.org/ Thanks, Jagadeesh > --- > bod
On 4/24/24 12:27, Jagadeesh Kona wrote: > > > On 4/24/2024 3:25 PM, Bryan O'Donoghue wrote: >> On 24/04/2024 10:47, Jagadeesh Kona wrote: >>> >>> >>> On 4/24/2024 5:18 AM, Bryan O'Donoghue wrote: >>>> On 13/04/2024 16:20, Jagadeesh Kona wrote: >>>>> Some GDSC client drivers require the GDSC mode to be switched dynamically >>>>> to HW mode at runtime to gain the power benefits. Typically such client >>>>> drivers require the GDSC to be brought up in SW mode initially to enable >>>>> the required dependent clocks and configure the hardware to proper state. >>>>> Once initial hardware set up is done, they switch the GDSC to HW mode to >>>>> save power. At the end of usecase, they switch the GDSC back to SW mode >>>>> and disable the GDSC. >>>>> >>>>> Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and >>>>> get_hwmode_dev callbacks for GDSC's whose respective client drivers >>>>> require the GDSC mode to be switched dynamically at runtime using >>>>> dev_pm_genpd_set_hwmode() API. >>>>> >>>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>>>> --- >>>>> drivers/clk/qcom/gdsc.c | 37 +++++++++++++++++++++++++++++++++++++ >>>>> drivers/clk/qcom/gdsc.h | 1 + >>>>> 2 files changed, 38 insertions(+) >>>>> >>>>> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c >>>>> index df9618ab7eea..c5f6be8181d8 100644 >>>>> --- a/drivers/clk/qcom/gdsc.c >>>>> +++ b/drivers/clk/qcom/gdsc.c >>>>> @@ -363,6 +363,39 @@ static int gdsc_disable(struct generic_pm_domain *domain) >>>>> return 0; >>>>> } >>>>> +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct device *dev, bool mode) >>>>> +{ >>>>> + struct gdsc *sc = domain_to_gdsc(domain); >>>>> + int ret; >>>>> + >>>>> + ret = gdsc_hwctrl(sc, mode); >>>>> + if (ret) >>>>> + return ret; >>>>> + >>>>> + /* Wait for 1usec for mode transition to properly complete */ >>>>> + udelay(1); >>>> >>>> A delay I suspect you don't need - if the HW spec says "takes 1 usec for this to take effect" that's 1 usec from io write completion from APSS to another system agent. >>>> >>>> You poll for the state transition down below anyway. >>>> >>>> I'd be pretty certain that's a redundant delay. >>>> >>> >>> Thanks Bryan for your review! >>> >>> This 1usec delay is needed every time GDSC is moved in and out of HW control mode and the reason for same is explained in one of the older gdsc driver change at below link >>> >>> https://lore.kernel.org/all/1484027679-18397-1-git-send-email-rnayak@codeaurora.org/ >>> >> >> Right. >> >> If that is your precedent then you seem to be missing the mb(); between >> >> gdsc_hwctrl(); >> >> /* mb(); here */ >> >> and this >> >> udelay(1); >> > > Sorry, earlier I shared the link to base patch series which has mb() used, but in the mainlined series of the same patch mb() is removed as per the review comments. > > Please find the mainlined series link:- > https://lore.kernel.org/all/1485145581-517-1-git-send-email-rnayak@codeaurora.org/ Mostly because mb is a solution to a different problem. See this talk for more details: https://youtu.be/i6DayghhA8Q Konrad
On 4/24/24 14:22, Konrad Dybcio wrote: > > > On 4/24/24 12:27, Jagadeesh Kona wrote: >> >> >> On 4/24/2024 3:25 PM, Bryan O'Donoghue wrote: >>> On 24/04/2024 10:47, Jagadeesh Kona wrote: >>>> >>>> >>>> On 4/24/2024 5:18 AM, Bryan O'Donoghue wrote: >>>>> On 13/04/2024 16:20, Jagadeesh Kona wrote: >>>>>> Some GDSC client drivers require the GDSC mode to be switched dynamically >>>>>> to HW mode at runtime to gain the power benefits. Typically such client >>>>>> drivers require the GDSC to be brought up in SW mode initially to enable >>>>>> the required dependent clocks and configure the hardware to proper state. >>>>>> Once initial hardware set up is done, they switch the GDSC to HW mode to >>>>>> save power. At the end of usecase, they switch the GDSC back to SW mode >>>>>> and disable the GDSC. >>>>>> >>>>>> Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and >>>>>> get_hwmode_dev callbacks for GDSC's whose respective client drivers >>>>>> require the GDSC mode to be switched dynamically at runtime using >>>>>> dev_pm_genpd_set_hwmode() API. >>>>>> >>>>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>>>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>>>>> --- >>>>>> drivers/clk/qcom/gdsc.c | 37 +++++++++++++++++++++++++++++++++++++ >>>>>> drivers/clk/qcom/gdsc.h | 1 + >>>>>> 2 files changed, 38 insertions(+) >>>>>> >>>>>> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c >>>>>> index df9618ab7eea..c5f6be8181d8 100644 >>>>>> --- a/drivers/clk/qcom/gdsc.c >>>>>> +++ b/drivers/clk/qcom/gdsc.c >>>>>> @@ -363,6 +363,39 @@ static int gdsc_disable(struct generic_pm_domain *domain) >>>>>> return 0; >>>>>> } >>>>>> +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct device *dev, bool mode) >>>>>> +{ >>>>>> + struct gdsc *sc = domain_to_gdsc(domain); >>>>>> + int ret; >>>>>> + >>>>>> + ret = gdsc_hwctrl(sc, mode); >>>>>> + if (ret) >>>>>> + return ret; >>>>>> + >>>>>> + /* Wait for 1usec for mode transition to properly complete */ >>>>>> + udelay(1); >>>>> >>>>> A delay I suspect you don't need - if the HW spec says "takes 1 usec for this to take effect" that's 1 usec from io write completion from APSS to another system agent. >>>>> >>>>> You poll for the state transition down below anyway. >>>>> >>>>> I'd be pretty certain that's a redundant delay. >>>>> >>>> >>>> Thanks Bryan for your review! >>>> >>>> This 1usec delay is needed every time GDSC is moved in and out of HW control mode and the reason for same is explained in one of the older gdsc driver change at below link >>>> >>>> https://lore.kernel.org/all/1484027679-18397-1-git-send-email-rnayak@codeaurora.org/ >>>> >>> >>> Right. >>> >>> If that is your precedent then you seem to be missing the mb(); between >>> >>> gdsc_hwctrl(); >>> >>> /* mb(); here */ >>> >>> and this >>> >>> udelay(1); >>> >> >> Sorry, earlier I shared the link to base patch series which has mb() used, but in the mainlined series of the same patch mb() is removed as per the review comments. >> >> Please find the mainlined series link:- >> https://lore.kernel.org/all/1485145581-517-1-git-send-email-rnayak@codeaurora.org/ > > Mostly because mb is a solution to a different problem. See this talk > for more details: > > https://youtu.be/i6DayghhA8Q (long story short: you want to read back the register right after writing to make sure things arrive at the hardware when you expect it to) Konrad
On 24.04.2024 11:50 AM, Bryan O'Donoghue wrote: > On 24/04/2024 10:45, Jagadeesh Kona wrote: >> >> Thanks Bryan for testing this series. Can you please confirm if this issue is observed in every run or only seen during the first run? Also please let me know on which platform this issue is observed? >> >> Thanks, >> Jagadeesh > > rb5/sm8250 > > My observation was on a previous _boot_ the stuttering was worse. There is in the video capture three times that I count where the video halts briefly, I guess we need to vote or set an OPP so the firmware knows not to power-collapse quite so aggressively. We seem to be having some qualcomm-wide variance on perf/pwr usage on some odd boots.. Any chance you could try like 5 times and see if it was a fluke? Konrad
On 30/04/2024 21:01, Konrad Dybcio wrote: > On 24.04.2024 11:50 AM, Bryan O'Donoghue wrote: >> On 24/04/2024 10:45, Jagadeesh Kona wrote: >>> >>> Thanks Bryan for testing this series. Can you please confirm if this issue is observed in every run or only seen during the first run? Also please let me know on which platform this issue is observed? >>> >>> Thanks, >>> Jagadeesh >> >> rb5/sm8250 >> >> My observation was on a previous _boot_ the stuttering was worse. There is in the video capture three times that I count where the video halts briefly, I guess we need to vote or set an OPP so the firmware knows not to power-collapse quite so aggressively. > > We seem to be having some qualcomm-wide variance on perf/pwr usage on some > odd boots.. Any chance you could try like 5 times and see if it was a fluke? > > Konrad Sure. The first time I tried it, it was much worse. The second time, captured in the video is only noticeable because I was *looking* for this specific error i.e. I don't think I would have noticed the error on the second run, had I not seen the first run. I'll find some time to do 5x with and 5x without. --- bod
On 01/05/2024 10:14, Bryan O'Donoghue wrote: > On 30/04/2024 21:01, Konrad Dybcio wrote: >> On 24.04.2024 11:50 AM, Bryan O'Donoghue wrote: >>> On 24/04/2024 10:45, Jagadeesh Kona wrote: >>>> >>>> Thanks Bryan for testing this series. Can you please confirm if this >>>> issue is observed in every run or only seen during the first run? >>>> Also please let me know on which platform this issue is observed? >>>> >>>> Thanks, >>>> Jagadeesh >>> >>> rb5/sm8250 >>> >>> My observation was on a previous _boot_ the stuttering was worse. >>> There is in the video capture three times that I count where the >>> video halts briefly, I guess we need to vote or set an OPP so the >>> firmware knows not to power-collapse quite so aggressively. >> >> We seem to be having some qualcomm-wide variance on perf/pwr usage on >> some >> odd boots.. Any chance you could try like 5 times and see if it was a >> fluke? >> >> Konrad > > Sure. > > The first time I tried it, it was much worse. > > The second time, captured in the video is only noticeable because I was > *looking* for this specific error i.e. I don't think I would have > noticed the error on the second run, had I not seen the first run. > > I'll find some time to do 5x with and 5x without. > > --- > bod ping bod please remember to do this thanks --- bod
On 5/10/2024 6:31 PM, Bryan O'Donoghue wrote: > On 01/05/2024 10:14, Bryan O'Donoghue wrote: >> On 30/04/2024 21:01, Konrad Dybcio wrote: >>> On 24.04.2024 11:50 AM, Bryan O'Donoghue wrote: >>>> On 24/04/2024 10:45, Jagadeesh Kona wrote: >>>>> >>>>> Thanks Bryan for testing this series. Can you please confirm if >>>>> this issue is observed in every run or only seen during the first >>>>> run? Also please let me know on which platform this issue is observed? >>>>> >>>>> Thanks, >>>>> Jagadeesh >>>> >>>> rb5/sm8250 >>>> >>>> My observation was on a previous _boot_ the stuttering was worse. >>>> There is in the video capture three times that I count where the >>>> video halts briefly, I guess we need to vote or set an OPP so the >>>> firmware knows not to power-collapse quite so aggressively. >>> >>> We seem to be having some qualcomm-wide variance on perf/pwr usage on >>> some >>> odd boots.. Any chance you could try like 5 times and see if it was a >>> fluke? >>> >>> Konrad >> >> Sure. >> >> The first time I tried it, it was much worse. >> >> The second time, captured in the video is only noticeable because I >> was *looking* for this specific error i.e. I don't think I would have >> noticed the error on the second run, had I not seen the first run. >> >> I'll find some time to do 5x with and 5x without. >> >> --- >> bod > > ping bod please remember to do this thanks > Hi Bryan, Could you please let me know if you got a chance to check the above? Thank you! Thanks, Jagadeesh
On 4/13/2024 8:50 PM, Jagadeesh Kona wrote: > Now that genpd supports dynamically switching the control for an > attached device between hardware- and software-mode, let's add this > information to the genpd summary under managed by column in debugfs. > > Suggested-by: Taniya Das<quic_tdas@quicinc.com> > Signed-off-by: Abel Vesa<abel.vesa@linaro.org> > Signed-off-by: Jagadeesh Kona<quic_jkona@quicinc.com> > Reviewed-by: Ulf Hansson<ulf.hansson@linaro.org> > Reviewed-by: Dmitry Baryshkov<dmitry.baryshkov@linaro.org> > Reviewed-by: Bjorn Andersson<andersson@kernel.org> > Reviewed-by: Dhruva Gole<d-gole@ti.com> > --- > drivers/pmdomain/core.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) Reviewed-by: Taniya Das <quic_tdas@quicinc.com>
On 6/17/2024 3:21 PM, Bryan O'Donoghue wrote: > On 17/06/2024 03:31, Jagadeesh Kona wrote: >> >> >> On 5/31/2024 5:26 PM, Jagadeesh Kona wrote: >>> >>> >>> On 5/10/2024 6:31 PM, Bryan O'Donoghue wrote: >>>> On 01/05/2024 10:14, Bryan O'Donoghue wrote: >>>>> On 30/04/2024 21:01, Konrad Dybcio wrote: >>>>>> On 24.04.2024 11:50 AM, Bryan O'Donoghue wrote: >>>>>>> On 24/04/2024 10:45, Jagadeesh Kona wrote: >>>>>>>> >>>>>>>> Thanks Bryan for testing this series. Can you please confirm if >>>>>>>> this issue is observed in every run or only seen during the >>>>>>>> first run? Also please let me know on which platform this issue >>>>>>>> is observed? >>>>>>>> >>>>>>>> Thanks, >>>>>>>> Jagadeesh >>>>>>> >>>>>>> rb5/sm8250 >>>>>>> >>>>>>> My observation was on a previous _boot_ the stuttering was worse. >>>>>>> There is in the video capture three times that I count where the >>>>>>> video halts briefly, I guess we need to vote or set an OPP so the >>>>>>> firmware knows not to power-collapse quite so aggressively. >>>>>> >>>>>> We seem to be having some qualcomm-wide variance on perf/pwr usage >>>>>> on some >>>>>> odd boots.. Any chance you could try like 5 times and see if it >>>>>> was a fluke? >>>>>> >>>>>> Konrad >>>>> >>>>> Sure. >>>>> >>>>> The first time I tried it, it was much worse. >>>>> >>>>> The second time, captured in the video is only noticeable because I >>>>> was *looking* for this specific error i.e. I don't think I would >>>>> have noticed the error on the second run, had I not seen the first >>>>> run. >>>>> >>>>> I'll find some time to do 5x with and 5x without. >>>>> >>>>> --- >>>>> bod >>>> >>>> ping bod please remember to do this thanks >>>> >>> >>> Hi Bryan, Could you please let me know if you got a chance to check >>> the above? Thank you! >>> >> >> Hi Bryan, Kindly can you please help confirm if this is a real issue >> or observed as a fluke? so we can go ahead and mainline these changes. >> >> Thanks, >> Jagadeesh > > So I'm happier with this patchset when I run gstreamer instead of ffmpeg. > > There doesn't appear to be a discernable difference between before/after > on framerate or subjective UX with/without this set. > > gst-launch-1.0 -vvv -e filesrc location=sample-5s.mp4 ! qtdemux ! > parsebin ! v4l2h264dec ! autovideosink > > Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Thanks a lot Bryan for helping with the testing. Thanks, Jagadeesh
This series adds support for dev_pm_genpd_set_hwmode() and dev_pm_genpd_get_hwmode() APIs and support in gdsc provider drivers to register respective callbacks and venus consumer driver example using above API to switch the power domain(GDSC) to HW/SW modes dynamically at runtime. This is resend of V5 series, added R-By tags received in V5 for 1st & 2nd patches. Link to V5: https://lore.kernel.org/all/20240315111046.22136-1-quic_jkona@quicinc.com/ Changes in V5: - Updated 1st patch as per V4 review comments to synchronize the initial HW mode state by invoking ->get_hwmode_dev()callback in genpd_add_device() - With above change, SW cached hwmode will contain correct value initially, and it will be updated everytime mode is changed in set_hwmode, hence updated dev_pm_genpd_get_hwmode() to just return SW cached hwmode in 1st patch - Updated commit text for 1st, 3rd, 4th and 5th patches - Updated 3rd and 5th patches as per review comments received on V4 series - Added R-By tags received in older series to 1st and 2nd patches Previous series: V4: https://lore.kernel.org/all/20240122-gdsc-hwctrl-v4-0-9061e8a7aa07@linaro.org/ V3: https://lore.kernel.org/lkml/20230823114528.3677667-1-abel.vesa@linaro.org/ V2: https://lore.kernel.org/lkml/20230816145741.1472721-1-abel.vesa@linaro.org/ V1: https://lore.kernel.org/all/20230628105652.1670316-1-abel.vesa@linaro.org/ Abel Vesa (1): PM: domains: Add the domain HW-managed mode to the summary Jagadeesh Kona (3): clk: qcom: gdsc: Add set and get hwmode callbacks to switch GDSC mode clk: qcom: Use HW_CTRL_TRIGGER flag to switch video GDSC to HW mode venus: pm_helpers: Use dev_pm_genpd_set_hwmode to switch GDSC mode on V6 Ulf Hansson (1): PM: domains: Allow devices attached to genpd to be managed by HW drivers/clk/qcom/gdsc.c | 37 +++++++++ drivers/clk/qcom/gdsc.h | 1 + drivers/clk/qcom/videocc-sc7280.c | 2 +- drivers/clk/qcom/videocc-sm8250.c | 4 +- .../media/platform/qcom/venus/pm_helpers.c | 39 ++++++---- drivers/pmdomain/core.c | 78 ++++++++++++++++++- include/linux/pm_domain.h | 17 ++++ 7 files changed, 157 insertions(+), 21 deletions(-)