| Message ID | 20240527211912.14060-5-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg/loongarch64: Support v64 and v256 | expand |
On 27/5/24 23:18, Richard Henderson wrote: > We can implement this with fld_d, fst_d for load and store, > and then use the normal v128 operations in registers. > This will improve support for guests which use v64. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/loongarch64/tcg-target.h | 2 +- > tcg/loongarch64/tcg-target.c.inc | 8 ++++++-- > 2 files changed, 7 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
在 2024/5/28 上午5:18, Richard Henderson 写道: > We can implement this with fld_d, fst_d for load and store, > and then use the normal v128 operations in registers. > This will improve support for guests which use v64. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/loongarch64/tcg-target.h | 2 +- > tcg/loongarch64/tcg-target.c.inc | 8 ++++++-- > 2 files changed, 7 insertions(+), 3 deletions(-) Reviewed-by: Song Gao <gaosong@loongson.cn> Thanks. Song Gao > diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h > index 29e4860d20..990bad1d51 100644 > --- a/tcg/loongarch64/tcg-target.h > +++ b/tcg/loongarch64/tcg-target.h > @@ -171,7 +171,7 @@ typedef enum { > > #define TCG_TARGET_HAS_tst 0 > > -#define TCG_TARGET_HAS_v64 0 > +#define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_LSX) > #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_LSX) > #define TCG_TARGET_HAS_v256 0 > > diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc > index de5369536e..980ea10211 100644 > --- a/tcg/loongarch64/tcg-target.c.inc > +++ b/tcg/loongarch64/tcg-target.c.inc > @@ -321,6 +321,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) > } > } > break; > + case TCG_TYPE_V64: > case TCG_TYPE_V128: > tcg_out_opc_vori_b(s, ret, arg, 0); > break; > @@ -838,6 +839,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg dest, > } > break; > case TCG_TYPE_I64: > + case TCG_TYPE_V64: > if (dest < TCG_REG_V0) { > tcg_out_ldst(s, OPC_LD_D, dest, base, offset); > } else { > @@ -869,6 +871,7 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src, > } > break; > case TCG_TYPE_I64: > + case TCG_TYPE_V64: > if (src < TCG_REG_V0) { > tcg_out_ldst(s, OPC_ST_D, src, base, offset); > } else { > @@ -1880,8 +1883,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, > a2 = args[2]; > a3 = args[3]; > > - /* Currently only supports V128 */ > - tcg_debug_assert(type == TCG_TYPE_V128); > + /* Currently only supports V64 & V128 */ > + tcg_debug_assert(type == TCG_TYPE_V64 || type == TCG_TYPE_V128); > > switch (opc) { > case INDEX_op_st_vec: > @@ -2394,6 +2397,7 @@ static void tcg_target_init(TCGContext *s) > tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); > > if (cpuinfo & CPUINFO_LSX) { > + tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; > tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; > tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24); > tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25);
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 29e4860d20..990bad1d51 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -171,7 +171,7 @@ typedef enum { #define TCG_TARGET_HAS_tst 0 -#define TCG_TARGET_HAS_v64 0 +#define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_LSX) #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_LSX) #define TCG_TARGET_HAS_v256 0 diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index de5369536e..980ea10211 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -321,6 +321,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) } } break; + case TCG_TYPE_V64: case TCG_TYPE_V128: tcg_out_opc_vori_b(s, ret, arg, 0); break; @@ -838,6 +839,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg dest, } break; case TCG_TYPE_I64: + case TCG_TYPE_V64: if (dest < TCG_REG_V0) { tcg_out_ldst(s, OPC_LD_D, dest, base, offset); } else { @@ -869,6 +871,7 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src, } break; case TCG_TYPE_I64: + case TCG_TYPE_V64: if (src < TCG_REG_V0) { tcg_out_ldst(s, OPC_ST_D, src, base, offset); } else { @@ -1880,8 +1883,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, a2 = args[2]; a3 = args[3]; - /* Currently only supports V128 */ - tcg_debug_assert(type == TCG_TYPE_V128); + /* Currently only supports V64 & V128 */ + tcg_debug_assert(type == TCG_TYPE_V64 || type == TCG_TYPE_V128); switch (opc) { case INDEX_op_st_vec: @@ -2394,6 +2397,7 @@ static void tcg_target_init(TCGContext *s) tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); if (cpuinfo & CPUINFO_LSX) { + tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25);
We can implement this with fld_d, fst_d for load and store, and then use the normal v128 operations in registers. This will improve support for guests which use v64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/loongarch64/tcg-target.h | 2 +- tcg/loongarch64/tcg-target.c.inc | 8 ++++++-- 2 files changed, 7 insertions(+), 3 deletions(-)