diff mbox series

[v3,3/3] usb: dwc3: core: Workaround for CSR read timeout

Message ID 20240611142953.12057-1-joswang1221@gmail.com
State Superseded
Headers show
Series None | expand

Commit Message

joswang June 11, 2024, 2:29 p.m. UTC
From: Jos Wang <joswang@lenovo.com>

This is a workaround for STAR 4846132, which only affects
DWC_usb31 version2.00a operating in host mode.

There is a problem in DWC_usb31 version 2.00a operating
in host mode that would cause a CSR read timeout When CSR
read coincides with RAM Clock Gating Entry. By disable
Clock Gating, sacrificing power consumption for normal
operation.

Signed-off-by: Jos Wang <joswang@lenovo.com>
---
v1 -> v2:
- add "dt-bindings: usb: dwc3: Add snps,p2p3tranok quirk" patch
v2 -> v3:
- code refactor
- modify comment, add STAR number, workaround applied in host mode
- modify commit message, add STAR number, workaround applied in host mode
- modify Author Jos Wang
---
 drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

Comments

Greg KH June 12, 2024, 7:58 a.m. UTC | #1
On Tue, Jun 11, 2024 at 10:29:53PM +0800, joswang wrote:
> From: Jos Wang <joswang@lenovo.com>
> 
> This is a workaround for STAR 4846132, which only affects
> DWC_usb31 version2.00a operating in host mode.
> 
> There is a problem in DWC_usb31 version 2.00a operating
> in host mode that would cause a CSR read timeout When CSR
> read coincides with RAM Clock Gating Entry. By disable
> Clock Gating, sacrificing power consumption for normal
> operation.
> 
> Signed-off-by: Jos Wang <joswang@lenovo.com>
> ---
> v1 -> v2:
> - add "dt-bindings: usb: dwc3: Add snps,p2p3tranok quirk" patch
> v2 -> v3:
> - code refactor
> - modify comment, add STAR number, workaround applied in host mode
> - modify commit message, add STAR number, workaround applied in host mode
> - modify Author Jos Wang
> ---
>  drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
>  1 file changed, 19 insertions(+), 1 deletion(-)

Should this have a cc: stable line?

thanks,

greg k-h
Greg KH June 12, 2024, 7:58 a.m. UTC | #2
On Tue, Jun 11, 2024 at 10:29:53PM +0800, joswang wrote:
> From: Jos Wang <joswang@lenovo.com>
> 
> This is a workaround for STAR 4846132, which only affects
> DWC_usb31 version2.00a operating in host mode.
> 
> There is a problem in DWC_usb31 version 2.00a operating
> in host mode that would cause a CSR read timeout When CSR
> read coincides with RAM Clock Gating Entry. By disable
> Clock Gating, sacrificing power consumption for normal
> operation.
> 
> Signed-off-by: Jos Wang <joswang@lenovo.com>
> ---
> v1 -> v2:
> - add "dt-bindings: usb: dwc3: Add snps,p2p3tranok quirk" patch
> v2 -> v3:
> - code refactor
> - modify comment, add STAR number, workaround applied in host mode
> - modify commit message, add STAR number, workaround applied in host mode
> - modify Author Jos Wang
> ---
>  drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
>  1 file changed, 19 insertions(+), 1 deletion(-)

Where are patches 1/3 and 2/3 of this series?

thanks,

greg k-h
joswang June 12, 2024, 12:44 p.m. UTC | #3
On Wed, Jun 12, 2024 at 3:58 PM Greg KH <gregkh@linuxfoundation.org> wrote:
>
> On Tue, Jun 11, 2024 at 10:29:53PM +0800, joswang wrote:
> > From: Jos Wang <joswang@lenovo.com>
> >
> > This is a workaround for STAR 4846132, which only affects
> > DWC_usb31 version2.00a operating in host mode.
> >
> > There is a problem in DWC_usb31 version 2.00a operating
> > in host mode that would cause a CSR read timeout When CSR
> > read coincides with RAM Clock Gating Entry. By disable
> > Clock Gating, sacrificing power consumption for normal
> > operation.
> >
> > Signed-off-by: Jos Wang <joswang@lenovo.com>
> > ---
> > v1 -> v2:
> > - add "dt-bindings: usb: dwc3: Add snps,p2p3tranok quirk" patch
> > v2 -> v3:
> > - code refactor
> > - modify comment, add STAR number, workaround applied in host mode
> > - modify commit message, add STAR number, workaround applied in host mode
> > - modify Author Jos Wang
> > ---
> >  drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
> >  1 file changed, 19 insertions(+), 1 deletion(-)
>
> Should this have a cc: stable line?
>
> thanks,
>
> greg k-h

Thanks for your help in reviewing the code.
In the subsequent v4 version, Cc: stable@vger.kernel.org will be added
to the patch approval area.

Thanks,

Jos Wang
joswang June 12, 2024, 12:47 p.m. UTC | #4
On Wed, Jun 12, 2024 at 3:58 PM Greg KH <gregkh@linuxfoundation.org> wrote:
>
> On Tue, Jun 11, 2024 at 10:29:53PM +0800, joswang wrote:
> > From: Jos Wang <joswang@lenovo.com>
> >
> > This is a workaround for STAR 4846132, which only affects
> > DWC_usb31 version2.00a operating in host mode.
> >
> > There is a problem in DWC_usb31 version 2.00a operating
> > in host mode that would cause a CSR read timeout When CSR
> > read coincides with RAM Clock Gating Entry. By disable
> > Clock Gating, sacrificing power consumption for normal
> > operation.
> >
> > Signed-off-by: Jos Wang <joswang@lenovo.com>
> > ---
> > v1 -> v2:
> > - add "dt-bindings: usb: dwc3: Add snps,p2p3tranok quirk" patch
> > v2 -> v3:
> > - code refactor
> > - modify comment, add STAR number, workaround applied in host mode
> > - modify commit message, add STAR number, workaround applied in host mode
> > - modify Author Jos Wang
> > ---
> >  drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
> >  1 file changed, 19 insertions(+), 1 deletion(-)
>
> Where are patches 1/3 and 2/3 of this series?
>
> thanks,
>
> greg k-h

Patches 1/3 and 2/3 are other cases. The maintainer is reviewing them
and has no accurate conclusion yet, so only patches 3/3 are submitted.

Thanks,

Jos Wang
Greg KH June 12, 2024, 12:56 p.m. UTC | #5
On Wed, Jun 12, 2024 at 08:47:31PM +0800, joswang wrote:
> On Wed, Jun 12, 2024 at 3:58 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> >
> > On Tue, Jun 11, 2024 at 10:29:53PM +0800, joswang wrote:
> > > From: Jos Wang <joswang@lenovo.com>
> > >
> > > This is a workaround for STAR 4846132, which only affects
> > > DWC_usb31 version2.00a operating in host mode.
> > >
> > > There is a problem in DWC_usb31 version 2.00a operating
> > > in host mode that would cause a CSR read timeout When CSR
> > > read coincides with RAM Clock Gating Entry. By disable
> > > Clock Gating, sacrificing power consumption for normal
> > > operation.
> > >
> > > Signed-off-by: Jos Wang <joswang@lenovo.com>
> > > ---
> > > v1 -> v2:
> > > - add "dt-bindings: usb: dwc3: Add snps,p2p3tranok quirk" patch
> > > v2 -> v3:
> > > - code refactor
> > > - modify comment, add STAR number, workaround applied in host mode
> > > - modify commit message, add STAR number, workaround applied in host mode
> > > - modify Author Jos Wang
> > > ---
> > >  drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
> > >  1 file changed, 19 insertions(+), 1 deletion(-)
> >
> > Where are patches 1/3 and 2/3 of this series?
> >
> > thanks,
> >
> > greg k-h
> 
> Patches 1/3 and 2/3 are other cases. The maintainer is reviewing them
> and has no accurate conclusion yet, so only patches 3/3 are submitted.

How are we supposed to know this?  A patch series should be taken all at
once, right?

confused,

greg k-h
joswang June 12, 2024, 1:39 p.m. UTC | #6
On Wed, Jun 12, 2024 at 8:56 PM Greg KH <gregkh@linuxfoundation.org> wrote:
>
> On Wed, Jun 12, 2024 at 08:47:31PM +0800, joswang wrote:
> > On Wed, Jun 12, 2024 at 3:58 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> > >
> > > On Tue, Jun 11, 2024 at 10:29:53PM +0800, joswang wrote:
> > > > From: Jos Wang <joswang@lenovo.com>
> > > >
> > > > This is a workaround for STAR 4846132, which only affects
> > > > DWC_usb31 version2.00a operating in host mode.
> > > >
> > > > There is a problem in DWC_usb31 version 2.00a operating
> > > > in host mode that would cause a CSR read timeout When CSR
> > > > read coincides with RAM Clock Gating Entry. By disable
> > > > Clock Gating, sacrificing power consumption for normal
> > > > operation.
> > > >
> > > > Signed-off-by: Jos Wang <joswang@lenovo.com>
> > > > ---
> > > > v1 -> v2:
> > > > - add "dt-bindings: usb: dwc3: Add snps,p2p3tranok quirk" patch
> > > > v2 -> v3:
> > > > - code refactor
> > > > - modify comment, add STAR number, workaround applied in host mode
> > > > - modify commit message, add STAR number, workaround applied in host mode
> > > > - modify Author Jos Wang
> > > > ---
> > > >  drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
> > > >  1 file changed, 19 insertions(+), 1 deletion(-)
> > >
> > > Where are patches 1/3 and 2/3 of this series?
> > >
> > > thanks,
> > >
> > > greg k-h
> >
> > Patches 1/3 and 2/3 are other cases. The maintainer is reviewing them
> > and has no accurate conclusion yet, so only patches 3/3 are submitted.
>
> How are we supposed to know this?  A patch series should be taken all at
> once, right?
>
> confused,
>
> greg k-h

I am very sorry, I misunderstood the patch series before. How should I
deal with this patch now? Should Patches 1/3 and 2/3 also be
submitted?
joswang June 12, 2024, 1:52 p.m. UTC | #7
On Wed, Jun 12, 2024 at 3:58 PM Greg KH <gregkh@linuxfoundation.org> wrote:
>
> On Tue, Jun 11, 2024 at 10:29:53PM +0800, joswang wrote:
> > From: Jos Wang <joswang@lenovo.com>
> >
> > This is a workaround for STAR 4846132, which only affects
> > DWC_usb31 version2.00a operating in host mode.
> >
> > There is a problem in DWC_usb31 version 2.00a operating
> > in host mode that would cause a CSR read timeout When CSR
> > read coincides with RAM Clock Gating Entry. By disable
> > Clock Gating, sacrificing power consumption for normal
> > operation.
> >
> > Signed-off-by: Jos Wang <joswang@lenovo.com>
> > ---
> > v1 -> v2:
> > - add "dt-bindings: usb: dwc3: Add snps,p2p3tranok quirk" patch
> > v2 -> v3:
> > - code refactor
> > - modify comment, add STAR number, workaround applied in host mode
> > - modify commit message, add STAR number, workaround applied in host mode
> > - modify Author Jos Wang
> > ---
> >  drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
> >  1 file changed, 19 insertions(+), 1 deletion(-)
>
> Should this have a cc: stable line?
>
> thanks,
>
> greg k-h

I have a question here, please help me confirm
1. Cc: stable@vger.kernel.org or Cc: stable@kernel.org ?
2. Do I need to modify the commit message, for example:
Cc: stable@kernel.org
Signed-off-by: Jos Wang <joswang@lenovo.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jos Wang <joswang@lenovo.com>
Greg KH June 12, 2024, 1:52 p.m. UTC | #8
On Wed, Jun 12, 2024 at 09:39:47PM +0800, joswang wrote:
> On Wed, Jun 12, 2024 at 8:56 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> >
> > On Wed, Jun 12, 2024 at 08:47:31PM +0800, joswang wrote:
> > > On Wed, Jun 12, 2024 at 3:58 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> > > >
> > > > On Tue, Jun 11, 2024 at 10:29:53PM +0800, joswang wrote:
> > > > > From: Jos Wang <joswang@lenovo.com>
> > > > >
> > > > > This is a workaround for STAR 4846132, which only affects
> > > > > DWC_usb31 version2.00a operating in host mode.
> > > > >
> > > > > There is a problem in DWC_usb31 version 2.00a operating
> > > > > in host mode that would cause a CSR read timeout When CSR
> > > > > read coincides with RAM Clock Gating Entry. By disable
> > > > > Clock Gating, sacrificing power consumption for normal
> > > > > operation.
> > > > >
> > > > > Signed-off-by: Jos Wang <joswang@lenovo.com>
> > > > > ---
> > > > > v1 -> v2:
> > > > > - add "dt-bindings: usb: dwc3: Add snps,p2p3tranok quirk" patch
> > > > > v2 -> v3:
> > > > > - code refactor
> > > > > - modify comment, add STAR number, workaround applied in host mode
> > > > > - modify commit message, add STAR number, workaround applied in host mode
> > > > > - modify Author Jos Wang
> > > > > ---
> > > > >  drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
> > > > >  1 file changed, 19 insertions(+), 1 deletion(-)
> > > >
> > > > Where are patches 1/3 and 2/3 of this series?
> > > >
> > > > thanks,
> > > >
> > > > greg k-h
> > >
> > > Patches 1/3 and 2/3 are other cases. The maintainer is reviewing them
> > > and has no accurate conclusion yet, so only patches 3/3 are submitted.
> >
> > How are we supposed to know this?  A patch series should be taken all at
> > once, right?
> >
> > confused,
> >
> > greg k-h
> 
> I am very sorry, I misunderstood the patch series before. How should I
> deal with this patch now? Should Patches 1/3 and 2/3 also be
> submitted?

Yes please.
Greg KH June 12, 2024, 2:07 p.m. UTC | #9
On Wed, Jun 12, 2024 at 09:52:04PM +0800, joswang wrote:
> On Wed, Jun 12, 2024 at 3:58 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> >
> > On Tue, Jun 11, 2024 at 10:29:53PM +0800, joswang wrote:
> > > From: Jos Wang <joswang@lenovo.com>
> > >
> > > This is a workaround for STAR 4846132, which only affects
> > > DWC_usb31 version2.00a operating in host mode.
> > >
> > > There is a problem in DWC_usb31 version 2.00a operating
> > > in host mode that would cause a CSR read timeout When CSR
> > > read coincides with RAM Clock Gating Entry. By disable
> > > Clock Gating, sacrificing power consumption for normal
> > > operation.
> > >
> > > Signed-off-by: Jos Wang <joswang@lenovo.com>
> > > ---
> > > v1 -> v2:
> > > - add "dt-bindings: usb: dwc3: Add snps,p2p3tranok quirk" patch
> > > v2 -> v3:
> > > - code refactor
> > > - modify comment, add STAR number, workaround applied in host mode
> > > - modify commit message, add STAR number, workaround applied in host mode
> > > - modify Author Jos Wang
> > > ---
> > >  drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
> > >  1 file changed, 19 insertions(+), 1 deletion(-)
> >
> > Should this have a cc: stable line?
> >
> > thanks,
> >
> > greg k-h
> 
> I have a question here, please help me confirm
> 1. Cc: stable@vger.kernel.org or Cc: stable@kernel.org ?
> 2. Do I need to modify the commit message, for example:
> Cc: stable@kernel.org
> Signed-off-by: Jos Wang <joswang@lenovo.com>
> Cc: stable@vger.kernel.org
> Signed-off-by: Jos Wang <joswang@lenovo.com>

Please read:
    https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html
for how to do this properly.
joswang June 12, 2024, 2:15 p.m. UTC | #10
On Wed, Jun 12, 2024 at 10:07 PM Greg KH <gregkh@linuxfoundation.org> wrote:
>
> On Wed, Jun 12, 2024 at 09:52:04PM +0800, joswang wrote:
> > On Wed, Jun 12, 2024 at 3:58 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> > >
> > > On Tue, Jun 11, 2024 at 10:29:53PM +0800, joswang wrote:
> > > > From: Jos Wang <joswang@lenovo.com>
> > > >
> > > > This is a workaround for STAR 4846132, which only affects
> > > > DWC_usb31 version2.00a operating in host mode.
> > > >
> > > > There is a problem in DWC_usb31 version 2.00a operating
> > > > in host mode that would cause a CSR read timeout When CSR
> > > > read coincides with RAM Clock Gating Entry. By disable
> > > > Clock Gating, sacrificing power consumption for normal
> > > > operation.
> > > >
> > > > Signed-off-by: Jos Wang <joswang@lenovo.com>
> > > > ---
> > > > v1 -> v2:
> > > > - add "dt-bindings: usb: dwc3: Add snps,p2p3tranok quirk" patch
> > > > v2 -> v3:
> > > > - code refactor
> > > > - modify comment, add STAR number, workaround applied in host mode
> > > > - modify commit message, add STAR number, workaround applied in host mode
> > > > - modify Author Jos Wang
> > > > ---
> > > >  drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
> > > >  1 file changed, 19 insertions(+), 1 deletion(-)
> > >
> > > Should this have a cc: stable line?
> > >
> > > thanks,
> > >
> > > greg k-h
> >
> > I have a question here, please help me confirm
> > 1. Cc: stable@vger.kernel.org or Cc: stable@kernel.org ?
> > 2. Do I need to modify the commit message, for example:
> > Cc: stable@kernel.org
> > Signed-off-by: Jos Wang <joswang@lenovo.com>
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Jos Wang <joswang@lenovo.com>
>
> Please read:
>     https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html
> for how to do this properly.

Thank You
diff mbox series

Patch

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 3a8fbc2d6b99..61f858f64e5a 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -960,12 +960,16 @@  static bool dwc3_core_is_valid(struct dwc3 *dwc)
 
 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 {
+	unsigned int power_opt;
+	unsigned int hw_mode;
 	u32 reg;
 
 	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+	hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+	power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
 
-	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
+	switch (power_opt) {
 	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 		/**
 		 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
@@ -998,6 +1002,20 @@  static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 		break;
 	}
 
+	/*
+	 * This is a workaround for STAR#4846132, which only affects
+	 * DWC_usb31 version2.00a operating in host mode.
+	 *
+	 * There is a problem in DWC_usb31 version 2.00a operating
+	 * in host mode that would cause a CSR read timeout When CSR
+	 * read coincides with RAM Clock Gating Entry. By disable
+	 * Clock Gating, sacrificing power consumption for normal
+	 * operation.
+	 */
+	if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO &&
+	    hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A))
+		reg |= DWC3_GCTL_DSBLCLKGTNG;
+
 	/* check if current dwc3 is on simulation board */
 	if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 		dev_info(dwc->dev, "Running with FPGA optimizations\n");