diff mbox series

[2/5] spi: cadence: Add Marvell IP modification changes

Message ID 20240329194849.25554-3-wsadowski@marvell.com
State Superseded
Headers show
Series Support for Cadence xSPI Marvell modifications | expand

Commit Message

Witold Sadowski March 29, 2024, 7:48 p.m. UTC 
Add support for Marvell IP modification - clock divider,
and PHY config, and IRQ clearing.
Clock divider block is build into Cadence XSPI controller
and is connected directly to 800MHz clock.
As PHY config is not set directly in IP block, driver can
load custom PHY configuration values.
To correctly clear interrupt in Marvell implementation
MSI-X must be cleared too.

Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
---
 drivers/spi/spi-cadence-xspi.c | 311 ++++++++++++++++++++++++++++++++-
 1 file changed, 306 insertions(+), 5 deletions(-)

Comments

Krzysztof Kozlowski March 30, 2024, 11:33 a.m. UTC | #1 
On 29/03/2024 20:48, Witold Sadowski wrote:
> Add support for Marvell IP modification - clock divider,
> and PHY config, and IRQ clearing.
> Clock divider block is build into Cadence XSPI controller
> and is connected directly to 800MHz clock.
> As PHY config is not set directly in IP block, driver can
> load custom PHY configuration values.
> To correctly clear interrupt in Marvell implementation
> MSI-X must be cleared too.

Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597

> 
> Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
> ---


> +
> +static bool cdns_xspi_get_hw_overlay(struct platform_device *pdev)
> +{
> +	int err;
> +
> +	err = device_property_match_string(&pdev->dev,
> +					   "compatible", "mrvl,xspi-nor");

No, do not add matching in some random parts of the code, but use driver
match/data from ID table.

....

>  
> +	cdns_xspi_print_phy_config(cdns_xspi);
>  	ret = cdns_xspi_controller_init(cdns_xspi);
>  	if (ret) {
>  		dev_err(dev, "Failed to initialize controller\n");
> @@ -613,6 +911,9 @@ static const struct of_device_id cdns_xspi_of_match[] = {
>  	{
>  		.compatible = "cdns,xspi-nor",
>  	},
> +	{
> +		.compatible = "mrvl,xspi-nor",

This falsely suggest they are compatible :/

> +	},
>  	{ /* end of table */}
>  };
>  MODULE_DEVICE_TABLE(of, cdns_xspi_of_match);

Best regards,
Krzysztof
kernel test robot March 31, 2024, 7:46 a.m. UTC | #2 
Hi Witold,

kernel test robot noticed the following build errors:

[auto build test ERROR on broonie-spi/for-next]
[also build test ERROR on linus/master v6.9-rc1 next-20240328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Witold-Sadowski/spi-cadence-Add-new-bindings-documentation-for-Cadence-XSPI/20240330-035124
base:   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link:    https://lore.kernel.org/r/20240329194849.25554-3-wsadowski%40marvell.com
patch subject: [PATCH 2/5] spi: cadence: Add Marvell IP modification changes
config: i386-randconfig-141-20240330 (https://download.01.org/0day-ci/archive/20240331/202403311540.oe0vVEdr-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240331/202403311540.oe0vVEdr-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403311540.oe0vVEdr-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/spi/spi-cadence-xspi.c:531:15: error: call to undeclared function 'readq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
     531 |                         *buf64++ = readq(addr);
         |                                    ^
   drivers/spi/spi-cadence-xspi.c:534:10: error: call to undeclared function 'readq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
     534 |                         tmp = readq(addr);
         |                               ^
   drivers/spi/spi-cadence-xspi.c:540:9: error: call to undeclared function 'readq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
     540 |                 tmp = readq(addr);
         |                       ^
>> drivers/spi/spi-cadence-xspi.c:555:4: error: call to undeclared function 'writeq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
     555 |                         writeq(*buf64++, addr);
         |                         ^
   drivers/spi/spi-cadence-xspi.c:559:4: error: call to undeclared function 'writeq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
     559 |                         writeq(tmp, addr);
         |                         ^
   drivers/spi/spi-cadence-xspi.c:565:3: error: call to undeclared function 'writeq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
     565 |                 writeq(tmp, addr);
         |                 ^
>> drivers/spi/spi-cadence-xspi.c:794:36: error: call to undeclared function 'spi_master_get_devdata'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
     794 |         struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(spi_dev->master);
         |                                           ^
   drivers/spi/spi-cadence-xspi.c:794:36: note: did you mean 'spi_mem_get_drvdata'?
   include/linux/spi/spi-mem.h:224:21: note: 'spi_mem_get_drvdata' declared here
     224 | static inline void *spi_mem_get_drvdata(struct spi_mem *mem)
         |                     ^
>> drivers/spi/spi-cadence-xspi.c:794:68: error: no member named 'master' in 'struct spi_device'
     794 |         struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(spi_dev->master);
         |                                                                  ~~~~~~~  ^
   8 errors generated.


vim +/readq +531 drivers/spi/spi-cadence-xspi.c

   520	
   521	static void mrvl_ioreadq(void __iomem  *addr, void *buf, int len)
   522	{
   523		int i = 0;
   524		int rcount = len / 8;
   525		int rcount_nf = len % 8;
   526		uint64_t tmp;
   527		uint64_t *buf64 = (uint64_t *)buf;
   528	
   529		if (((uint64_t)buf % 8) == 0) {
   530			for (i = 0; i < rcount; i++)
 > 531				*buf64++ = readq(addr);
   532		} else {
   533			for (i = 0; i < rcount; i++) {
   534				tmp = readq(addr);
   535				memcpy(buf+(i*8), &tmp, 8);
   536			}
   537		}
   538	
   539		if (rcount_nf != 0) {
   540			tmp = readq(addr);
   541			memcpy(buf+(i*8), &tmp, rcount_nf);
   542		}
   543	}
   544	
   545	static void mrvl_iowriteq(void __iomem *addr, const void *buf, int len)
   546	{
   547		int i = 0;
   548		int rcount = len / 8;
   549		int rcount_nf = len % 8;
   550		uint64_t tmp;
   551		uint64_t *buf64 = (uint64_t *)buf;
   552	
   553		if (((uint64_t)buf % 8) == 0) {
   554			for (i = 0; i < rcount; i++)
 > 555				writeq(*buf64++, addr);
   556		} else {
   557			for (i = 0; i < rcount; i++) {
   558				memcpy(&tmp, buf+(i*8), 8);
   559				writeq(tmp, addr);
   560			}
   561		}
   562	
   563		if (rcount_nf != 0) {
   564			memcpy(&tmp, buf+(i*8), rcount_nf);
   565			writeq(tmp, addr);
   566		}
   567	}
   568
Krzysztof Kozlowski March 31, 2024, 10:50 a.m. UTC | #3 
On 29/03/2024 20:48, Witold Sadowski wrote:
> Add support for Marvell IP modification - clock divider,
> and PHY config, and IRQ clearing.
> Clock divider block is build into Cadence XSPI controller
> and is connected directly to 800MHz clock.
> As PHY config is not set directly in IP block, driver can
> load custom PHY configuration values.
> To correctly clear interrupt in Marvell implementation
> MSI-X must be cleared too.
> 
> Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
> ---
>  drivers/spi/spi-cadence-xspi.c | 311 ++++++++++++++++++++++++++++++++-

You already sent this patchset, so this is not v1. Please version your
patches correctly. b4 does it automatically.

You also received last time feedback which it seems you just ignored.
You did not respond to any of the feedback and I do not see it being
addressed here.

That's not how collaboration in upstream projects work. Don't just
ignore reviews you receive. Please carefully read:

https://elixir.bootlin.com/linux/v6.9-rc1/source/Documentation/process/submitting-patches.rst

There is also entire section about this particular issue - responding to
reviewers.

Best regards,
Krzysztof
Witold Sadowski April 29, 2024, 2:55 p.m. UTC | #4 
> ----------------------------------------------------------------------
> On 29/03/2024 20:48, Witold Sadowski wrote:
> > Add support for Marvell IP modification - clock divider, and PHY
> > config, and IRQ clearing.
> > Clock divider block is build into Cadence XSPI controller and is
> > connected directly to 800MHz clock.
> > As PHY config is not set directly in IP block, driver can load custom
> > PHY configuration values.
> > To correctly clear interrupt in Marvell implementation MSI-X must be
> > cleared too.
> 
> Please wrap commit message according to Linux coding style / submission
> process (neither too early nor over the limit):
> https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__elixir.bootlin.com_linux_v6.4-
> 2Drc1_source_Documentation_process_submitting-2Dpatches.rst-
> 23L597&d=DwICaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=GKgcn-g6ZX-
> JmCL3S2qKgVQhvhv7hu2n8En-
> dZbLTa8&m=jNf5MYEcexHML6io2koiqn18Pmkh2qqc0FL48zdCoojbFX06omzl2_Z0CpBeHn79
> &s=B038dgBUB0Gvl63ExMDFoXuomZBSZPHLpScHOtTax0Q&e=
> 
> >
> > Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
> > ---
> 
> 
> > +
> > +static bool cdns_xspi_get_hw_overlay(struct platform_device *pdev) {
> > +	int err;
> > +
> > +	err = device_property_match_string(&pdev->dev,
> > +					   "compatible", "mrvl,xspi-nor");
> 
> No, do not add matching in some random parts of the code, but use driver
> match/data from ID table.

Ok. As I have written in different mail, a little bit of manual matching
Will be necessary to handle both ACPI and device-tree case.

> 
> ....
> 
> >
> > +	cdns_xspi_print_phy_config(cdns_xspi);
> >  	ret = cdns_xspi_controller_init(cdns_xspi);
> >  	if (ret) {
> >  		dev_err(dev, "Failed to initialize controller\n"); @@ -613,6
> +911,9
> > @@ static const struct of_device_id cdns_xspi_of_match[] = {
> >  	{
> >  		.compatible = "cdns,xspi-nor",
> >  	},
> > +	{
> > +		.compatible = "mrvl,xspi-nor",
> 
> This falsely suggest they are compatible :/

I'm not sure if I understand what do you mean.
cdns, xspi will be compatible with overlay, as it won't touch any
additional HW. It possibly fail in second direction, as overlay
handling code will not see expected values.

> 
> > +	},
> >  	{ /* end of table */}
> >  };
> >  MODULE_DEVICE_TABLE(of, cdns_xspi_of_match);
> 
> Best regards,
> Krzysztof

Regards
Witek
Krzysztof Kozlowski April 30, 2024, 7:56 a.m. UTC | #5 
On 29/04/2024 16:55, Witold Sadowski wrote:
>>
>>> +
>>> +static bool cdns_xspi_get_hw_overlay(struct platform_device *pdev) {
>>> +	int err;
>>> +
>>> +	err = device_property_match_string(&pdev->dev,
>>> +					   "compatible", "mrvl,xspi-nor");
>>
>> No, do not add matching in some random parts of the code, but use driver
>> match/data from ID table.
> 
> Ok. As I have written in different mail, a little bit of manual matching
> Will be necessary to handle both ACPI and device-tree case.

ACPI also handle variants with match data.

> 
>>
>> ....
>>
>>>
>>> +	cdns_xspi_print_phy_config(cdns_xspi);
>>>  	ret = cdns_xspi_controller_init(cdns_xspi);
>>>  	if (ret) {
>>>  		dev_err(dev, "Failed to initialize controller\n"); @@ -613,6
>> +911,9
>>> @@ static const struct of_device_id cdns_xspi_of_match[] = {
>>>  	{
>>>  		.compatible = "cdns,xspi-nor",
>>>  	},
>>> +	{
>>> +		.compatible = "mrvl,xspi-nor",
>>
>> This falsely suggest they are compatible :/
> 
> I'm not sure if I understand what do you mean.
> cdns, xspi will be compatible with overlay, as it won't touch any
> additional HW. It possibly fail in second direction, as overlay
> handling code will not see expected values.

That's clear rule for almost every driver: if you do not have any match
data, it suggests entry is redundant, because devices are compatible.
There is no different treatment for SPI. As seen in other pieces of this
code, devices are not compatible, so it points to missing match data to
handle variants.

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c
index 8648b8eb080d..f570b2920b18 100644
--- a/drivers/spi/spi-cadence-xspi.c
+++ b/drivers/spi/spi-cadence-xspi.c
@@ -189,6 +189,43 @@ 
 		((op)->data.dir == SPI_MEM_DATA_IN) ? \
 		CDNS_XSPI_STIG_CMD_DIR_READ : CDNS_XSPI_STIG_CMD_DIR_WRITE))
 
+/*PHY default values*/
+#define REGS_DLL_PHY_CTRL		0x00000707
+#define CTB_RFILE_PHY_CTRL		0x00004000
+#define RFILE_PHY_TSEL			0x00000000
+#define RFILE_PHY_DQ_TIMING		0x00000101
+#define RFILE_PHY_DQS_TIMING		0x00700404
+#define RFILE_PHY_GATE_LPBK_CTRL	0x00200030
+#define RFILE_PHY_DLL_MASTER_CTRL	0x00800000
+#define RFILE_PHY_DLL_SLAVE_CTRL	0x0000ff01
+
+/*PHY config rtegisters*/
+#define CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL			0x1034
+#define CDNS_XSPI_PHY_CTB_RFILE_PHY_CTRL			0x0080
+#define CDNS_XSPI_PHY_CTB_RFILE_PHY_TSEL			0x0084
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQ_TIMING		0x0000
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQS_TIMING		0x0004
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL	0x0008
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL	0x000c
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL	0x0010
+#define CDNS_XSPI_DATASLICE_RFILE_PHY_DLL_OBS_REG_0		0x001c
+
+#define CDNS_XSPI_DLL_RST_N BIT(24)
+#define CDNS_XSPI_DLL_LOCK  BIT(0)
+
+/* Marvell clock config register */
+#define CDNS_MRVL_XSPI_CLK_CTRL_AUX_REG	0x2020
+#define CDNS_MRVL_XSPI_CLK_ENABLE	BIT(0)
+#define CDNS_MRVL_XSPI_CLK_DIV		GENMASK(4, 1)
+
+/* Marvell MSI-X clear interrupt register */
+#define CDNS_MRVL_XSPI_SPIX_INTR_AUX	0x2000
+#define CDNS_MRVL_MSIX_CLEAR_IRQ	0x01
+
+/* Marvell clock macros */
+#define CDNS_MRVL_XSPI_CLOCK_IO_HZ 800000000
+#define CDNS_MRVL_XSPI_CLOCK_DIVIDED(div) ((CDNS_MRVL_XSPI_CLOCK_IO_HZ) / (div))
+
 enum cdns_xspi_stig_instr_type {
 	CDNS_XSPI_STIG_INSTR_TYPE_0,
 	CDNS_XSPI_STIG_INSTR_TYPE_1,
@@ -208,6 +245,7 @@  enum cdns_xspi_stig_cmd_dir {
 struct cdns_xspi_dev {
 	struct platform_device *pdev;
 	struct device *dev;
+	bool mrvl_hw_overlay;
 
 	void __iomem *iobase;
 	void __iomem *auxbase;
@@ -228,6 +266,157 @@  struct cdns_xspi_dev {
 	u8 hw_num_banks;
 };
 
+#define MRVL_DEFAULT_CLK 25000000
+
+const int cdns_mrvl_xspi_clk_div_list[] = {
+	4,	//0x0 = Divide by 4.   SPI clock is 200 MHz.
+	6,	//0x1 = Divide by 6.   SPI clock is 133.33 MHz.
+	8,	//0x2 = Divide by 8.   SPI clock is 100 MHz.
+	10,	//0x3 = Divide by 10.  SPI clock is 80 MHz.
+	12,	//0x4 = Divide by 12.  SPI clock is 66.666 MHz.
+	16,	//0x5 = Divide by 16.  SPI clock is 50 MHz.
+	18,	//0x6 = Divide by 18.  SPI clock is 44.44 MHz.
+	20,	//0x7 = Divide by 20.  SPI clock is 40 MHz.
+	24,	//0x8 = Divide by 24.  SPI clock is 33.33 MHz.
+	32,	//0x9 = Divide by 32.  SPI clock is 25 MHz.
+	40,	//0xA = Divide by 40.  SPI clock is 20 MHz.
+	50,	//0xB = Divide by 50.  SPI clock is 16 MHz.
+	64,	//0xC = Divide by 64.  SPI clock is 12.5 MHz.
+	128,	//0xD = Divide by 128. SPI clock is 6.25 MHz.
+	-1	//End of list
+};
+
+static bool cdns_xspi_reset_dll(struct cdns_xspi_dev *cdns_xspi)
+{
+	u32 dll_cntrl = readl(cdns_xspi->iobase +
+			      CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL);
+	u32 dll_lock;
+
+	/*Reset DLL*/
+	dll_cntrl |= CDNS_XSPI_DLL_RST_N;
+	writel(dll_cntrl, cdns_xspi->iobase +
+			  CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL);
+
+	/*Wait for DLL lock*/
+	return readl_relaxed_poll_timeout(cdns_xspi->iobase +
+		CDNS_XSPI_INTR_STATUS_REG,
+		dll_lock, ((dll_lock & CDNS_XSPI_DLL_LOCK) == 1), 10, 10000);
+}
+
+static void cdns_configure_phy_register_io(struct cdns_xspi_dev *cdns_xspi,
+					   const char *prop_name,
+					   u64 default_value, u64 offset)
+{
+	struct device_node *node_prop = cdns_xspi->pdev->dev.of_node;
+	u64 phy_cfg;
+
+	if (of_property_read_u64(node_prop, prop_name, &phy_cfg))
+		phy_cfg = default_value;
+	writel(phy_cfg,
+		cdns_xspi->iobase + offset);
+}
+
+static void cdns_configure_phy_register_aux(struct cdns_xspi_dev *cdns_xspi,
+					    const char *prop_name,
+					    u64 default_value, u64 offset)
+{
+	struct device_node *node_prop = cdns_xspi->pdev->dev.of_node;
+	u64 phy_cfg;
+
+	if (of_property_read_u64(node_prop, "cdns,dll-phy-control", &phy_cfg))
+		phy_cfg = default_value;
+	writel(phy_cfg,
+		cdns_xspi->auxbase + offset);
+}
+
+//Static confiuration of PHY
+static bool cdns_xspi_configure_phy(struct cdns_xspi_dev *cdns_xspi)
+{
+	cdns_configure_phy_register_io(cdns_xspi,
+				       "cdns,dll-phy-control",
+				       REGS_DLL_PHY_CTRL,
+				       CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL);
+	cdns_configure_phy_register_aux(cdns_xspi,
+					"cdns,rfile-phy-control",
+					CTB_RFILE_PHY_CTRL,
+					CDNS_XSPI_PHY_CTB_RFILE_PHY_CTRL);
+	cdns_configure_phy_register_aux(cdns_xspi,
+					"cdns,rfile-phy-tsel",
+					RFILE_PHY_TSEL,
+					CDNS_XSPI_PHY_CTB_RFILE_PHY_TSEL);
+	cdns_configure_phy_register_aux(cdns_xspi,
+				"cdns,phy-dq-timing",
+				RFILE_PHY_DQ_TIMING,
+				CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQ_TIMING);
+	cdns_configure_phy_register_aux(cdns_xspi,
+			"cdns,phy-dqs-timing",
+			RFILE_PHY_DQS_TIMING,
+			CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQS_TIMING);
+	cdns_configure_phy_register_aux(cdns_xspi,
+			"cdns,phy-gate-lpbk-ctrl",
+			RFILE_PHY_GATE_LPBK_CTRL,
+			CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL);
+	cdns_configure_phy_register_aux(cdns_xspi,
+			"cdns,phy-dll-master-ctrl",
+			RFILE_PHY_DLL_MASTER_CTRL,
+			CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL);
+	cdns_configure_phy_register_aux(cdns_xspi,
+			"cdns,phy-dll-slave-ctrl",
+			RFILE_PHY_DLL_SLAVE_CTRL,
+			CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL);
+
+	return cdns_xspi_reset_dll(cdns_xspi);
+}
+
+// Find max avalible clock
+static bool cdns_mrvl_xspi_setup_clock(struct cdns_xspi_dev *cdns_xspi,
+				       int requested_clk)
+{
+	int i = 0;
+	int clk_val;
+	u32 clk_reg;
+	bool update_clk = false;
+
+	while (cdns_mrvl_xspi_clk_div_list[i] > 0) {
+		clk_val = CDNS_MRVL_XSPI_CLOCK_DIVIDED(
+				cdns_mrvl_xspi_clk_div_list[i]);
+		if (clk_val <= requested_clk)
+			break;
+		i++;
+	}
+
+	if (cdns_mrvl_xspi_clk_div_list[i] == -1) {
+		dev_info(cdns_xspi->dev,
+			"Unable to find clk div for CLK: %d - using 6.25MHz\n",
+		       requested_clk);
+		i = 0x0D;
+	} else {
+		dev_dbg(cdns_xspi->dev, "Found clk div: %d, clk val: %d\n",
+			cdns_mrvl_xspi_clk_div_list[i],
+			CDNS_MRVL_XSPI_CLOCK_DIVIDED(
+				cdns_mrvl_xspi_clk_div_list[i]));
+	}
+
+	clk_reg = readl(cdns_xspi->auxbase + CDNS_MRVL_XSPI_CLK_CTRL_AUX_REG);
+
+	if (FIELD_GET(CDNS_MRVL_XSPI_CLK_DIV, clk_reg) != i) {
+		clk_reg &= ~CDNS_MRVL_XSPI_CLK_ENABLE;
+		writel(clk_reg,
+		       cdns_xspi->auxbase + CDNS_MRVL_XSPI_CLK_CTRL_AUX_REG);
+		clk_reg = FIELD_PREP(CDNS_MRVL_XSPI_CLK_DIV, i);
+		clk_reg &= ~CDNS_MRVL_XSPI_CLK_DIV;
+		clk_reg |= FIELD_PREP(CDNS_MRVL_XSPI_CLK_DIV, i);
+		clk_reg |= CDNS_MRVL_XSPI_CLK_ENABLE;
+		update_clk = true;
+	}
+
+	if (update_clk)
+		writel(clk_reg,
+		       cdns_xspi->auxbase + CDNS_MRVL_XSPI_CLK_CTRL_AUX_REG);
+
+	return update_clk;
+}
+
 static int cdns_xspi_wait_for_controller_idle(struct cdns_xspi_dev *cdns_xspi)
 {
 	u32 ctrl_stat;
@@ -291,6 +480,10 @@  static void cdns_xspi_set_interrupts(struct cdns_xspi_dev *cdns_xspi,
 				     bool enabled)
 {
 	u32 intr_enable;
+	u32 irq_status;
+
+	irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
+	writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
 
 	intr_enable = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
 	if (enabled)
@@ -315,6 +508,9 @@  static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi)
 		return -EIO;
 	}
 
+	writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE, CDNS_XSPI_WORK_MODE_STIG),
+	       cdns_xspi->iobase + CDNS_XSPI_CTRL_CONFIG_REG);
+
 	ctrl_features = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_FEATURES_REG);
 	cdns_xspi->hw_num_banks = FIELD_GET(CDNS_XSPI_NUM_BANKS, ctrl_features);
 	cdns_xspi_set_interrupts(cdns_xspi, false);
@@ -322,6 +518,70 @@  static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi)
 	return 0;
 }
 
+static void mrvl_ioreadq(void __iomem  *addr, void *buf, int len)
+{
+	int i = 0;
+	int rcount = len / 8;
+	int rcount_nf = len % 8;
+	uint64_t tmp;
+	uint64_t *buf64 = (uint64_t *)buf;
+
+	if (((uint64_t)buf % 8) == 0) {
+		for (i = 0; i < rcount; i++)
+			*buf64++ = readq(addr);
+	} else {
+		for (i = 0; i < rcount; i++) {
+			tmp = readq(addr);
+			memcpy(buf+(i*8), &tmp, 8);
+		}
+	}
+
+	if (rcount_nf != 0) {
+		tmp = readq(addr);
+		memcpy(buf+(i*8), &tmp, rcount_nf);
+	}
+}
+
+static void mrvl_iowriteq(void __iomem *addr, const void *buf, int len)
+{
+	int i = 0;
+	int rcount = len / 8;
+	int rcount_nf = len % 8;
+	uint64_t tmp;
+	uint64_t *buf64 = (uint64_t *)buf;
+
+	if (((uint64_t)buf % 8) == 0) {
+		for (i = 0; i < rcount; i++)
+			writeq(*buf64++, addr);
+	} else {
+		for (i = 0; i < rcount; i++) {
+			memcpy(&tmp, buf+(i*8), 8);
+			writeq(tmp, addr);
+		}
+	}
+
+	if (rcount_nf != 0) {
+		memcpy(&tmp, buf+(i*8), rcount_nf);
+		writeq(tmp, addr);
+	}
+}
+
+static void cdns_xspi_sdma_memread(struct cdns_xspi_dev *cdns_xspi, int len)
+{
+	if (cdns_xspi->mrvl_hw_overlay)
+		mrvl_ioreadq(cdns_xspi->sdmabase, cdns_xspi->in_buffer, len);
+	else
+		ioread8_rep(cdns_xspi->sdmabase, cdns_xspi->in_buffer, len);
+}
+
+static void cdns_xspi_sdma_memwrite(struct cdns_xspi_dev *cdns_xspi, int len)
+{
+	if (cdns_xspi->mrvl_hw_overlay)
+		mrvl_iowriteq(cdns_xspi->sdmabase, cdns_xspi->out_buffer, len);
+	else
+		iowrite8_rep(cdns_xspi->sdmabase, cdns_xspi->out_buffer, len);
+}
+
 static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
 {
 	u32 sdma_size, sdma_trd_info;
@@ -333,13 +593,11 @@  static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
 
 	switch (sdma_dir) {
 	case CDNS_XSPI_SDMA_DIR_READ:
-		ioread8_rep(cdns_xspi->sdmabase,
-			    cdns_xspi->in_buffer, sdma_size);
+		cdns_xspi_sdma_memread(cdns_xspi, sdma_size);
 		break;
 
 	case CDNS_XSPI_SDMA_DIR_WRITE:
-		iowrite8_rep(cdns_xspi->sdmabase,
-			     cdns_xspi->out_buffer, sdma_size);
+		cdns_xspi_sdma_memwrite(cdns_xspi, sdma_size);
 		break;
 	}
 }
@@ -411,6 +669,9 @@  static int cdns_xspi_mem_op(struct cdns_xspi_dev *cdns_xspi,
 	if (cdns_xspi->cur_cs != spi_get_chipselect(mem->spi, 0))
 		cdns_xspi->cur_cs = spi_get_chipselect(mem->spi, 0);
 
+	if (cdns_xspi->mrvl_hw_overlay)
+		cdns_mrvl_xspi_setup_clock(cdns_xspi, mem->spi->max_speed_hz);
+
 	return cdns_xspi_send_stig_command(cdns_xspi, op,
 					   (dir != SPI_MEM_NO_DATA));
 }
@@ -451,6 +712,10 @@  static irqreturn_t cdns_xspi_irq_handler(int this_irq, void *dev)
 	irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
 	writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
 
+	if (cdns_xspi->mrvl_hw_overlay)
+		writel(CDNS_MRVL_MSIX_CLEAR_IRQ,
+		       cdns_xspi->auxbase + CDNS_MRVL_XSPI_SPIX_INTR_AUX);
+
 	if (irq_status &
 	    (CDNS_XSPI_SDMA_ERROR | CDNS_XSPI_SDMA_TRIGGER |
 	     CDNS_XSPI_STIG_DONE)) {
@@ -524,6 +789,27 @@  static void cdns_xspi_print_phy_config(struct cdns_xspi_dev *cdns_xspi)
 		 readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL));
 }
 
+static int cdns_xspi_setup(struct spi_device *spi_dev)
+{
+	struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(spi_dev->master);
+
+	if (cdns_xspi->mrvl_hw_overlay)
+		cdns_mrvl_xspi_setup_clock(cdns_xspi, spi_dev->max_speed_hz);
+
+	return 0;
+}
+
+static bool cdns_xspi_get_hw_overlay(struct platform_device *pdev)
+{
+	int err;
+
+	err = device_property_match_string(&pdev->dev,
+					   "compatible", "mrvl,xspi-nor");
+
+
+	return (err >= 0);
+}
+
 static int cdns_xspi_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -531,6 +817,7 @@  static int cdns_xspi_probe(struct platform_device *pdev)
 	struct cdns_xspi_dev *cdns_xspi = NULL;
 	struct resource *res;
 	int ret;
+	bool hw_overlay;
 
 	host = devm_spi_alloc_host(dev, sizeof(*cdns_xspi));
 	if (!host)
@@ -540,10 +827,15 @@  static int cdns_xspi_probe(struct platform_device *pdev)
 		SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL | SPI_RX_OCTAL |
 		SPI_MODE_0  | SPI_MODE_3;
 
+	hw_overlay = cdns_xspi_get_hw_overlay(pdev);
+
 	host->mem_ops = &cadence_xspi_mem_ops;
 	host->dev.of_node = pdev->dev.of_node;
 	host->bus_num = -1;
 
+	if (hw_overlay)
+		host->setup = cdns_xspi_setup;
+
 	platform_set_drvdata(pdev, host);
 
 	cdns_xspi = spi_controller_get_devdata(host);
@@ -555,6 +847,8 @@  static int cdns_xspi_probe(struct platform_device *pdev)
 	init_completion(&cdns_xspi->auto_cmd_complete);
 	init_completion(&cdns_xspi->sdma_complete);
 
+	cdns_xspi->mrvl_hw_overlay = hw_overlay;
+
 	ret = cdns_xspi_of_get_plat_data(pdev);
 	if (ret)
 		return -ENODEV;
@@ -588,8 +882,12 @@  static int cdns_xspi_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	cdns_xspi_print_phy_config(cdns_xspi);
+	if (hw_overlay) {
+		cdns_mrvl_xspi_setup_clock(cdns_xspi, MRVL_DEFAULT_CLK);
+		cdns_xspi_configure_phy(cdns_xspi);
+	}
 
+	cdns_xspi_print_phy_config(cdns_xspi);
 	ret = cdns_xspi_controller_init(cdns_xspi);
 	if (ret) {
 		dev_err(dev, "Failed to initialize controller\n");
@@ -613,6 +911,9 @@  static const struct of_device_id cdns_xspi_of_match[] = {
 	{
 		.compatible = "cdns,xspi-nor",
 	},
+	{
+		.compatible = "mrvl,xspi-nor",
+	},
 	{ /* end of table */}
 };
 MODULE_DEVICE_TABLE(of, cdns_xspi_of_match);