| Message ID | 20240424024508.3857602-1-quic_tengfan@quicinc.com |
|---|---|
| Headers | show |
| Series | arm64: qcom: add AIM300 AIoT board support | expand |
On Wed, 24 Apr 2024 10:45:04 +0800, Tengfei Fan wrote: > Add AIM300 AIoT support along with usb, ufs, regulators, serial, PCIe, > and PMIC functions. > AIM300 Series is a highly optimized family of modules designed to > support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC > chip etc. > Here is a diagram of AIM300 AIoT Carrie Board and SoM > +--------------------------------------------------+ > | AIM300 AIOT Carrier Board | > | | > | +-----------------+ | > |power----->| Fixed regulator |---------+ | > | +-----------------+ | | > | | | > | v VPH_PWR | > | +----------------------------------------------+ | > | | AIM300 SOM | | | > | | |VPH_PWR | | > | | v | | > | | +-------+ +--------+ +------+ | | > | | | UFS | | QCS8550| |PMIC | | | > | | +-------+ +--------+ +------+ | | > | | | | > | +----------------------------------------------+ | > | | > | +----+ +------+ | > | |USB | | UART | | > | +----+ +------+ | > +--------------------------------------------------+ > The following functions have been verified: > - uart > - usb > - ufs > - PCIe > - PMIC > - display > - adsp > - cdsp > - tlmm > > Documentation for qcs8550[1] and sm8550[2] > [1] https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf > [2] https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/Snapdragon-8-Gen-2-Product-Brief.pdf > > Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> > --- > > v6 -> v7: > - correct typos in the commit message > - move mdss_dsi0, mdss_dsi0_phy, pcie0_phy, pcie1_phy and usb_dp_qmpphy > vdda supply to qcs8550-aim300.dtsi > - move the perst and wake gpio settings of pcie0 and pcie1 to > qcs8550-aim300.dtsi > - move the clock frequency settings of pcie_1_phy_aux_clk, sleep_clk > and xo_board to qcs8550-aim300.dtsi > - verified with dtb check, and result is expected, because those > warnings are not introduced by current patch series. > arch/arm64/boot/dts/qcom/sm8550.dtsi:3037.27-3092.6: Warning > (avoid_unnecessary_addr_size): /soc@0/display-subsystem@ae00000/dsi@ae96000: unnecessary > #address-cells/#size-cells without "ranges" or child "reg" property > arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: > phy@1c0e000: clock-output-names: ['pcie1_pipe_clk'] is too short > from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# > arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: phy@1c0e000: #clock-cells:0:0: 1 was expected > from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# > > v5 -> v6: > - move qcs8550 board info bebind sm8550 boards info in qcom.yaml > > v4 -> v5: > - "2023-2024" instead of "2023~2024" for License > - update patch commit message to previous comments and with an updated > board diagram > - use qcs8550.dtsi instead of qcm8550.dtsi > - remove the reserved memory regions which will be handled by > bootloader > - remove pm8550_flash, pm8550_pwm nodes, Type-C USB/DP function node, > remoteproc_mpss function node, audio sound DTS node, new patch will > be updated after respective team's end to end full verification > - address comments to vph_pwr, move vph_pwr node and related > references to qcs8550-aim300-aiot.dts > - use "regulator-vph-pwr" instead of "vph_pwr_regulator" > - add pcie0I AND pcie1 support together > - the following patches were applied, so remove these patches from new > patch series: > - https://lore.kernel.org/linux-arm-msm/20240119100621.11788-3-quic_tengfan@quicinc.com > - https://lore.kernel.org/linux-arm-msm/20240119100621.11788-4-quic_tengfan@quicinc.com > - verified with dtb check, and result is expected, because those > warnings are not introduced by current patch series. > DTC_CHK arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb > arch/arm64/boot/dts/qcom/sm8550.dtsi:3015.27-3070.6: Warning > (avoid_unnecessary_addr_size): /soc@0/display-subsystem@ae00000/dsi@ae96000: unnecessary > #address-cells/#size-cells without "ranges" or child "reg" property > arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: > opp-table: opp-75000000:opp-hz:0: [75000000, 0, 0, 75000000, 0, 0, 0, 0] is too long > from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml# > arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: > opp-table: opp-150000000:opp-hz:0: [150000000, 0, 0, 150000000, 0, 0, 0, 0] is too long > from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml# > arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: > opp-table: opp-300000000:opp-hz:0: [300000000, 0, 0, 300000000, 0, 0, 0, 0] is too long > from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml# > arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: > opp-table: Unevaluated properties are not allowed ('opp-150000000', 'opp-300000000', 'opp-75000000' were unexpected) > from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml# > > v3 -> v4: > - use qcm8550.dtsi instead of qcs8550.dtsi, qcs8550 is a QCS version > of qcm8550, another board with qcm8550 will be added later > - add AIM300 AIoT board string in qcom.yaml file > - add sm8550 and qcm8550 fallback compatible > - add qcm8550 SoC id > - add reserved memory map codes in qcm8550.dtsi > - pm8010 and pmr73d are splited into carrier board DTS file. Because > the regulators which in pm8550, pm8550ve and pm8550vs are present > on the SoM. The regulators which in pm8010 and pmr73d are present > on the carrier board. > - stay VPH_PWR at qcs8550-aim300.dtsi file > VPH_PWR is obtained by vonverting 12v voltage into 3.7 voltage > with a 3.7v buck. VPH_PWR is power supply for regulators in AIM300 > SOM. VPH_PWR regulator is defined in AIM300 SOM dtsi file. > > v2 -> v3: > - introduce qcs8550.dtsi > - separate fix dtc W=1 warning patch to another patch series > > v1 -> v2: > - merge the splited dts patches into one patch > - update dts file name from qcom8550-aim300.dts to qcs8550-aim300 dts > - drop PCIe1 dts node due to it is not enabled > - update display node name for drop sde characters > > previous discussion here: > [1] v6 RESEND: https://lore.kernel.org/linux-arm-msm/20240401093843.2591147-1-quic_tengfan@quicinc.com > [2] v6: https://lore.kernel.org/linux-arm-msm/20240308070432.28195-1-quic_tengfan@quicinc.com > [3] v5: https://lore.kernel.org/linux-arm-msm/20240301134113.14423-1-quic_tengfan@quicinc.com > [4] v4: https://lore.kernel.org/linux-arm-msm/20240119100621.11788-1-quic_tengfan@quicinc.com > [5] v3: https://lore.kernel.org/linux-arm-msm/20231219005007.11644-1-quic_tengfan@quicinc.com > [6] v2: https://lore.kernel.org/linux-arm-msm/20231207092801.7506-1-quic_tengfan@quicinc.com > [7] v1: https://lore.kernel.org/linux-arm-msm/20231117101817.4401-1-quic_tengfan@quicinc.com > > Tengfei Fan (4): > dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board > arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi > arm64: dts: qcom: add base AIM300 dtsi > arm64: dts: qcom: aim300: add AIM300 AIoT > > .../devicetree/bindings/arm/qcom.yaml | 8 + > arch/arm64/boot/dts/qcom/Makefile | 1 + > .../boot/dts/qcom/qcs8550-aim300-aiot.dts | 343 +++++++++++++++ > arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 403 ++++++++++++++++++ > arch/arm64/boot/dts/qcom/qcs8550.dtsi | 169 ++++++++ > 5 files changed, 924 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts > create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi > create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi > > > base-commit: a59668a9397e7245b26e9be85d23f242ff757ae8 > -- > 2.25.1 > > > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade New warnings running 'make CHECK_DTBS=y qcom/qcs8550-aim300-aiot.dtb' for 20240424024508.3857602-1-quic_tengfan@quicinc.com: arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: phy@1c0e000: clock-output-names: ['pcie1_pipe_clk'] is too short from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: phy@1c0e000: #clock-cells:0:0: 1 was expected from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
On Wed, 24 Apr 2024 at 05:46, Tengfei Fan <quic_tengfan@quicinc.com> wrote: > > AIM300 Series is a highly optimized family of modules designed to > support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC > chip etc. > Here is a diagram of AIM300 SoM: > +----------------------------------------+ > |AIM300 SoM | > | | > | +-----+ | > | |--->| UFS | | > | | +-----+ | > | | | > | | | > 3.7v | +-----------------+ | +---------+ | > ---------->| PMIC |----->| QCS8550 | | > | +-----------------+ +---------+ | > | | | > | | | > | | +-----+ | > | |--->| ... | | > | +-----+ | > | | > +----------------------------------------+ > > Co-developed-by: Fenglin Wu <quic_fenglinw@quicinc.com> > Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com> > Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 403 +++++++++++++++++++ > 1 file changed, 403 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi > + > +&pcie_1_phy_aux_clk { > + clock-frequency = <1000>; > +}; Please rebase on top of https://lore.kernel.org/linux-arm-msm/20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v4-0-868b15a17a45@linaro.org/ > + > +&pcie1 { > + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; Please add pinctrl configurations for pcie0 and pcie1 With that fixed: Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > +}; > + > -- With best wishes Dmitry
On 4/25/2024 7:47 AM, Dmitry Baryshkov wrote: > On Wed, 24 Apr 2024 at 05:46, Tengfei Fan <quic_tengfan@quicinc.com> wrote: >> >> AIM300 Series is a highly optimized family of modules designed to >> support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC >> chip etc. >> Here is a diagram of AIM300 SoM: >> +----------------------------------------+ >> |AIM300 SoM | >> | | >> | +-----+ | >> | |--->| UFS | | >> | | +-----+ | >> | | | >> | | | >> 3.7v | +-----------------+ | +---------+ | >> ---------->| PMIC |----->| QCS8550 | | >> | +-----------------+ +---------+ | >> | | | >> | | | >> | | +-----+ | >> | |--->| ... | | >> | +-----+ | >> | | >> +----------------------------------------+ >> >> Co-developed-by: Fenglin Wu <quic_fenglinw@quicinc.com> >> Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com> >> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 403 +++++++++++++++++++ >> 1 file changed, 403 insertions(+) >> create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi > > >> + >> +&pcie_1_phy_aux_clk { >> + clock-frequency = <1000>; >> +}; > > Please rebase on top of > https://lore.kernel.org/linux-arm-msm/20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v4-0-868b15a17a45@linaro.org/ Sure, I will reabse on the top of this patch series in the new version patch series > >> + >> +&pcie1 { >> + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; >> + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; > > Please add pinctrl configurations for pcie0 and pcie1 > > With that fixed: > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> The pinctrl configurations of pcie0 and pcie1 will be moved to this dtsi file from Carrier Board dts file. > >> +}; >> + >> > > -- > With best wishes > Dmitry
Add AIM300 AIoT support along with usb, ufs, regulators, serial, PCIe, and PMIC functions. AIM300 Series is a highly optimized family of modules designed to support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC chip etc. Here is a diagram of AIM300 AIoT Carrie Board and SoM +--------------------------------------------------+ | AIM300 AIOT Carrier Board | | | | +-----------------+ | |power----->| Fixed regulator |---------+ | | +-----------------+ | | | | | | v VPH_PWR | | +----------------------------------------------+ | | | AIM300 SOM | | | | | |VPH_PWR | | | | v | | | | +-------+ +--------+ +------+ | | | | | UFS | | QCS8550| |PMIC | | | | | +-------+ +--------+ +------+ | | | | | | | +----------------------------------------------+ | | | | +----+ +------+ | | |USB | | UART | | | +----+ +------+ | +--------------------------------------------------+ The following functions have been verified: - uart - usb - ufs - PCIe - PMIC - display - adsp - cdsp - tlmm Documentation for qcs8550[1] and sm8550[2] [1] https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf [2] https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/Snapdragon-8-Gen-2-Product-Brief.pdf Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> --- v6 -> v7: - correct typos in the commit message - move mdss_dsi0, mdss_dsi0_phy, pcie0_phy, pcie1_phy and usb_dp_qmpphy vdda supply to qcs8550-aim300.dtsi - move the perst and wake gpio settings of pcie0 and pcie1 to qcs8550-aim300.dtsi - move the clock frequency settings of pcie_1_phy_aux_clk, sleep_clk and xo_board to qcs8550-aim300.dtsi - verified with dtb check, and result is expected, because those warnings are not introduced by current patch series. arch/arm64/boot/dts/qcom/sm8550.dtsi:3037.27-3092.6: Warning (avoid_unnecessary_addr_size): /soc@0/display-subsystem@ae00000/dsi@ae96000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: phy@1c0e000: clock-output-names: ['pcie1_pipe_clk'] is too short from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: phy@1c0e000: #clock-cells:0:0: 1 was expected from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# v5 -> v6: - move qcs8550 board info bebind sm8550 boards info in qcom.yaml v4 -> v5: - "2023-2024" instead of "2023~2024" for License - update patch commit message to previous comments and with an updated board diagram - use qcs8550.dtsi instead of qcm8550.dtsi - remove the reserved memory regions which will be handled by bootloader - remove pm8550_flash, pm8550_pwm nodes, Type-C USB/DP function node, remoteproc_mpss function node, audio sound DTS node, new patch will be updated after respective team's end to end full verification - address comments to vph_pwr, move vph_pwr node and related references to qcs8550-aim300-aiot.dts - use "regulator-vph-pwr" instead of "vph_pwr_regulator" - add pcie0I AND pcie1 support together - the following patches were applied, so remove these patches from new patch series: - https://lore.kernel.org/linux-arm-msm/20240119100621.11788-3-quic_tengfan@quicinc.com - https://lore.kernel.org/linux-arm-msm/20240119100621.11788-4-quic_tengfan@quicinc.com - verified with dtb check, and result is expected, because those warnings are not introduced by current patch series. DTC_CHK arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb arch/arm64/boot/dts/qcom/sm8550.dtsi:3015.27-3070.6: Warning (avoid_unnecessary_addr_size): /soc@0/display-subsystem@ae00000/dsi@ae96000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: opp-table: opp-75000000:opp-hz:0: [75000000, 0, 0, 75000000, 0, 0, 0, 0] is too long from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml# arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: opp-table: opp-150000000:opp-hz:0: [150000000, 0, 0, 150000000, 0, 0, 0, 0] is too long from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml# arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: opp-table: opp-300000000:opp-hz:0: [300000000, 0, 0, 300000000, 0, 0, 0, 0] is too long from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml# arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: opp-table: Unevaluated properties are not allowed ('opp-150000000', 'opp-300000000', 'opp-75000000' were unexpected) from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml# v3 -> v4: - use qcm8550.dtsi instead of qcs8550.dtsi, qcs8550 is a QCS version of qcm8550, another board with qcm8550 will be added later - add AIM300 AIoT board string in qcom.yaml file - add sm8550 and qcm8550 fallback compatible - add qcm8550 SoC id - add reserved memory map codes in qcm8550.dtsi - pm8010 and pmr73d are splited into carrier board DTS file. Because the regulators which in pm8550, pm8550ve and pm8550vs are present on the SoM. The regulators which in pm8010 and pmr73d are present on the carrier board. - stay VPH_PWR at qcs8550-aim300.dtsi file VPH_PWR is obtained by vonverting 12v voltage into 3.7 voltage with a 3.7v buck. VPH_PWR is power supply for regulators in AIM300 SOM. VPH_PWR regulator is defined in AIM300 SOM dtsi file. v2 -> v3: - introduce qcs8550.dtsi - separate fix dtc W=1 warning patch to another patch series v1 -> v2: - merge the splited dts patches into one patch - update dts file name from qcom8550-aim300.dts to qcs8550-aim300 dts - drop PCIe1 dts node due to it is not enabled - update display node name for drop sde characters previous discussion here: [1] v6 RESEND: https://lore.kernel.org/linux-arm-msm/20240401093843.2591147-1-quic_tengfan@quicinc.com [2] v6: https://lore.kernel.org/linux-arm-msm/20240308070432.28195-1-quic_tengfan@quicinc.com [3] v5: https://lore.kernel.org/linux-arm-msm/20240301134113.14423-1-quic_tengfan@quicinc.com [4] v4: https://lore.kernel.org/linux-arm-msm/20240119100621.11788-1-quic_tengfan@quicinc.com [5] v3: https://lore.kernel.org/linux-arm-msm/20231219005007.11644-1-quic_tengfan@quicinc.com [6] v2: https://lore.kernel.org/linux-arm-msm/20231207092801.7506-1-quic_tengfan@quicinc.com [7] v1: https://lore.kernel.org/linux-arm-msm/20231117101817.4401-1-quic_tengfan@quicinc.com Tengfei Fan (4): dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi arm64: dts: qcom: add base AIM300 dtsi arm64: dts: qcom: aim300: add AIM300 AIoT .../devicetree/bindings/arm/qcom.yaml | 8 + arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/qcs8550-aim300-aiot.dts | 343 +++++++++++++++ arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 403 ++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs8550.dtsi | 169 ++++++++ 5 files changed, 924 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi base-commit: a59668a9397e7245b26e9be85d23f242ff757ae8