| Message ID | 20240408132925.1880571-1-quic_kriskura@quicinc.com |
|---|---|
| Headers | show |
| Series | Add multiport support for DWC3 controllers | expand |
On Mon, Apr 08, 2024, Krishna Kurapati wrote: > Currently the DWC3 driver supports only single port controller > which requires at least one HS PHY and at most one SS PHY. > > But the DWC3 USB controller can be connected to multiple ports and > each port can have their own PHYs. Each port of the multiport > controller can either be HS+SS capable or HS only capable > Proper quantification of them is required to modify GUSB2PHYCFG > and GUSB3PIPECTL registers appropriately. > > Add support for detecting, obtaining and configuring PHYs supported > by a multiport controller. Limit support to multiport controllers > with up to four ports for now (e.g. as needed for SC8280XP). > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Johan Hovold <johan+linaro@kernel.org> > --- > drivers/usb/dwc3/core.c | 251 ++++++++++++++++++++++++++++------------ > drivers/usb/dwc3/core.h | 14 ++- > drivers/usb/dwc3/drd.c | 15 ++- > 3 files changed, 193 insertions(+), 87 deletions(-) > <snip> > @@ -1937,6 +2020,10 @@ static int dwc3_get_num_ports(struct dwc3 *dwc) > > iounmap(base); > > + if (dwc->num_usb2_ports > DWC3_MAX_PORTS || > + dwc->num_usb3_ports > DWC3_MAX_PORTS) > + return -ENOMEM; This should be -EINVAL. > + > return 0; > } <snip> > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h > index 341e4c73cb2e..df2e111aa848 100644 > --- a/drivers/usb/dwc3/core.h > +++ b/drivers/usb/dwc3/core.h > @@ -33,6 +33,12 @@ > > #include <linux/power_supply.h> > > +/* > + * Maximum number of ports currently supported for multiport > + * controllers. This macro here is being used per USB2 vs USB3 ports rather than USB2 + USB3, unlike the xHCI MAXPORTS. You can clarify in the comment and rename the macro to avoid any confusion. You can also create 2 separate macros for number of USB2 and USB3 ports even if they share the same value. As noted[*], we support have different max number of usb2 ports vs usb3 ports. I would suggest splitting the macros. [*] https://lore.kernel.org/linux-usb/20230801013031.ft3zpoatiyfegmh6@synopsys.com/ > + */ > +#define DWC3_MAX_PORTS 4 > + > But it's not a big issue whether you decided to push a new version or a create a separate patch for the comments above. Here's my Ack: Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Thanks, Thinh
On Mon, Apr 08, 2024, Krishna Kurapati wrote: > On multiport supported controllers, each port has its own DP/DM > and SS (if super speed capable) interrupts. As per the bindings, > their interrupt names differ from standard ones having "_x" added > as suffix (x indicates port number). Identify from the interrupt > names whether the controller is a multiport controller or not. > Refactor dwc3_qcom_setup_irq() call to parse multiport interrupts > along with non-multiport ones accordingly.. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Johan Hovold <johan+linaro@kernel.org> > --- > drivers/usb/dwc3/dwc3-qcom.c | 137 ++++++++++++++++++++++++++--------- > 1 file changed, 103 insertions(+), 34 deletions(-) > > diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c > index cae5dab8fcfc..35eb338514bc 100644 > --- a/drivers/usb/dwc3/dwc3-qcom.c > +++ b/drivers/usb/dwc3/dwc3-qcom.c > @@ -52,6 +52,13 @@ > #define APPS_USB_AVG_BW 0 > #define APPS_USB_PEAK_BW MBps_to_icc(40) > > +struct dwc3_qcom_port { > + int qusb2_phy_irq; > + int dp_hs_phy_irq; > + int dm_hs_phy_irq; > + int ss_phy_irq; > +}; > + > struct dwc3_qcom { > struct device *dev; > void __iomem *qscratch_base; > @@ -59,11 +66,8 @@ struct dwc3_qcom { > struct clk **clks; > int num_clocks; > struct reset_control *resets; > - > - int qusb2_phy_irq; > - int dp_hs_phy_irq; > - int dm_hs_phy_irq; > - int ss_phy_irq; > + struct dwc3_qcom_port ports[DWC3_MAX_PORTS]; > + u8 num_ports; > enum usb_device_speed usb2_speed; > > struct extcon_dev *edev; > @@ -354,24 +358,24 @@ static void dwc3_qcom_disable_wakeup_irq(int irq) > > static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) > { > - dwc3_qcom_disable_wakeup_irq(qcom->qusb2_phy_irq); > + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].qusb2_phy_irq); > > if (qcom->usb2_speed == USB_SPEED_LOW) { > - dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); > + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq); > } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || > (qcom->usb2_speed == USB_SPEED_FULL)) { > - dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); > + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq); > } else { > - dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); > - dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); > + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq); > + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq); > } > > - dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq); > + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].ss_phy_irq); > } > > static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) > { > - dwc3_qcom_enable_wakeup_irq(qcom->qusb2_phy_irq, 0); > + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].qusb2_phy_irq, 0); > > /* > * Configure DP/DM line interrupts based on the USB2 device attached to > @@ -383,20 +387,20 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) > */ > > if (qcom->usb2_speed == USB_SPEED_LOW) { > - dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, > - IRQ_TYPE_EDGE_FALLING); > + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq, > + IRQ_TYPE_EDGE_FALLING); > } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || > (qcom->usb2_speed == USB_SPEED_FULL)) { > - dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, > - IRQ_TYPE_EDGE_FALLING); > + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq, > + IRQ_TYPE_EDGE_FALLING); > } else { > - dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, > - IRQ_TYPE_EDGE_RISING); > - dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, > - IRQ_TYPE_EDGE_RISING); > + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq, > + IRQ_TYPE_EDGE_RISING); > + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq, > + IRQ_TYPE_EDGE_RISING); > } > > - dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0); > + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].ss_phy_irq, 0); > } > > static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) > @@ -517,42 +521,107 @@ static int dwc3_qcom_request_irq(struct dwc3_qcom *qcom, int irq, > return ret; > } > > -static int dwc3_qcom_setup_irq(struct platform_device *pdev) > +static int dwc3_qcom_setup_port_irq(struct platform_device *pdev, int port_index, bool is_multiport) > { > struct dwc3_qcom *qcom = platform_get_drvdata(pdev); > + const char *irq_name; > int irq; > int ret; > > - irq = platform_get_irq_byname_optional(pdev, "qusb2_phy"); > + if (is_multiport) > + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_%d", port_index + 1); > + else > + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_irq"); > + if (!irq_name) > + return -ENOMEM; > + > + irq = platform_get_irq_byname_optional(pdev, irq_name); > if (irq > 0) { > - ret = dwc3_qcom_request_irq(qcom, irq, "qusb2_phy"); > + ret = dwc3_qcom_request_irq(qcom, irq, irq_name); > if (ret) > return ret; > - qcom->qusb2_phy_irq = irq; > + qcom->ports[port_index].dp_hs_phy_irq = irq; > } > > - irq = platform_get_irq_byname_optional(pdev, "dp_hs_phy_irq"); > + if (is_multiport) > + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_%d", port_index + 1); > + else > + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_irq"); > + if (!irq_name) > + return -ENOMEM; > + > + irq = platform_get_irq_byname_optional(pdev, irq_name); > if (irq > 0) { > - ret = dwc3_qcom_request_irq(qcom, irq, "dp_hs_phy_irq"); > + ret = dwc3_qcom_request_irq(qcom, irq, irq_name); > if (ret) > return ret; > - qcom->dp_hs_phy_irq = irq; > + qcom->ports[port_index].dm_hs_phy_irq = irq; > } > > - irq = platform_get_irq_byname_optional(pdev, "dm_hs_phy_irq"); > + if (is_multiport) > + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_%d", port_index + 1); > + else > + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_irq"); > + if (!irq_name) > + return -ENOMEM; > + > + irq = platform_get_irq_byname_optional(pdev, irq_name); > if (irq > 0) { > - ret = dwc3_qcom_request_irq(qcom, irq, "dm_hs_phy_irq"); > + ret = dwc3_qcom_request_irq(qcom, irq, irq_name); > if (ret) > return ret; > - qcom->dm_hs_phy_irq = irq; > + qcom->ports[port_index].ss_phy_irq = irq; > } > > - irq = platform_get_irq_byname_optional(pdev, "ss_phy_irq"); > + if (is_multiport) > + return 0; > + > + irq = platform_get_irq_byname_optional(pdev, "qusb2_phy"); > if (irq > 0) { > - ret = dwc3_qcom_request_irq(qcom, irq, "ss_phy_irq"); > + ret = dwc3_qcom_request_irq(qcom, irq, "qusb2_phy"); > + if (ret) > + return ret; > + qcom->ports[port_index].qusb2_phy_irq = irq; > + } > + > + return 0; > +} > + > +static int dwc3_qcom_find_num_ports(struct platform_device *pdev) > +{ > + char irq_name[14]; > + int port_num; > + int irq; > + > + irq = platform_get_irq_byname_optional(pdev, "dp_hs_phy_1"); > + if (irq <= 0) > + return 1; > + > + for (port_num = 2; port_num <= DWC3_MAX_PORTS; port_num++) { > + sprintf(irq_name, "dp_hs_phy_%d", port_num); > + > + irq = platform_get_irq_byname_optional(pdev, irq_name); > + if (irq <= 0) > + return port_num - 1; > + } > + > + return DWC3_MAX_PORTS; > +} > + > +static int dwc3_qcom_setup_irq(struct platform_device *pdev) > +{ > + struct dwc3_qcom *qcom = platform_get_drvdata(pdev); > + bool is_multiport; > + int ret; > + int i; > + > + qcom->num_ports = dwc3_qcom_find_num_ports(pdev); > + is_multiport = (qcom->num_ports > 1); > + > + for (i = 0; i < qcom->num_ports; i++) { > + ret = dwc3_qcom_setup_port_irq(pdev, i, is_multiport); > if (ret) > return ret; > - qcom->ss_phy_irq = irq; > } > > return 0; > -- > 2.34.1 > Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Thanks, Thinh
On 4/9/2024 6:41 AM, Thinh Nguyen wrote: > On Mon, Apr 08, 2024, Krishna Kurapati wrote: >> Currently the DWC3 driver supports only single port controller >> which requires at least one HS PHY and at most one SS PHY. >> >> But the DWC3 USB controller can be connected to multiple ports and >> each port can have their own PHYs. Each port of the multiport >> controller can either be HS+SS capable or HS only capable >> Proper quantification of them is required to modify GUSB2PHYCFG >> and GUSB3PIPECTL registers appropriately. >> >> Add support for detecting, obtaining and configuring PHYs supported >> by a multiport controller. Limit support to multiport controllers >> with up to four ports for now (e.g. as needed for SC8280XP). >> >> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> >> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> >> --- >> drivers/usb/dwc3/core.c | 251 ++++++++++++++++++++++++++++------------ >> drivers/usb/dwc3/core.h | 14 ++- >> drivers/usb/dwc3/drd.c | 15 ++- >> 3 files changed, 193 insertions(+), 87 deletions(-) >> > > <snip> > >> @@ -1937,6 +2020,10 @@ static int dwc3_get_num_ports(struct dwc3 *dwc) >> >> iounmap(base); >> >> + if (dwc->num_usb2_ports > DWC3_MAX_PORTS || >> + dwc->num_usb3_ports > DWC3_MAX_PORTS) >> + return -ENOMEM; > > This should be -EINVAL. > >> + >> return 0; >> } > > <snip> > >> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h >> index 341e4c73cb2e..df2e111aa848 100644 >> --- a/drivers/usb/dwc3/core.h >> +++ b/drivers/usb/dwc3/core.h >> @@ -33,6 +33,12 @@ >> >> #include <linux/power_supply.h> >> >> +/* >> + * Maximum number of ports currently supported for multiport >> + * controllers. > > This macro here is being used per USB2 vs USB3 ports rather than USB2 + > USB3, unlike the xHCI MAXPORTS. You can clarify in the comment and > rename the macro to avoid any confusion. You can also create 2 separate > macros for number of USB2 and USB3 ports even if they share the same > value. > > As noted[*], we support have different max number of usb2 ports vs usb3 > ports. I would suggest splitting the macros. > Hi Thinh, This macro was intended only to identify how many USB2 (or USB3) Phy's were serviced/operated by this driver, not how many logical ports present (like in xHCI). I don't think it would be confusing currently given that it is only used to identify number of generic phy instances to allocate and not used for any other purpose. Once the num_usb2_ports and num_usb3_ports are read by get_num_ports(...) call, they directly indicate how many ports are HS and SS respectively. Keeping the same in mind, I returned ENOMEM above (as you mentioned) because we don't allocate more than DWC3_MAX_PORTS and if the number of hs or ss ports is more than that, we simply return ENOMEM saying the driver doesn't support operating those many phy's. > [*] https://lore.kernel.org/linux-usb/20230801013031.ft3zpoatiyfegmh6@synopsys.com/ > >> + */ >> +#define DWC3_MAX_PORTS 4 >> + >> > > But it's not a big issue whether you decided to push a new version or a > create a separate patch for the comments above. Here's my Ack: > Since this is not a bug, I would prefer to make a separate patch to rename the macros. (If that is fine). > Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> > > Thanks, > Thinh
Currently the DWC3 driver supports only single port controller which requires at most two PHYs ie HS and SS PHYs. There are SoCs that has DWC3 controller with multiple ports that can operate in host mode. Some of the port supports both SS+HS and other port supports only HS mode. This change primarily refactors the Phy logic in core driver to allow multiport support with Generic Phy's. Changes have been tested on QCOM SoC SA8295P which has 4 ports (2 are HS+SS capable and 2 are HS only capable). Changes in v20: Modified return check in get_num_ports call. Code re-verified internally and added Bjorn.A RB Tag in patch (2/9) from internal review. Changes in v19: Replaced IS_ERR(ptr) with a NULL check. Modified name of function reading the port num in core file. Changes in v18: Updated variable names in patch-7 for setup_port_irq and find_num_ports calls. Changes in v17: Modified DT handling patch by checking if dp_hs_phy_1 is present or not and then going for DT parsing. Changes in v16: Removing ACPI has simplified the interrupt reading in wrapper. Also the logic to find number of ports is based on dp_hs_phy interrupt check in DT. Enabling and disabling interrupts is now done per port. Added info on power event irq in commit message. Changes in v15: Added minItems property in qcom,dwc3 bindings as suggested by Rob. Retained all RB's/ACK's got in v14. Changes in v14: Moved wrapper binding update to 5th patch in the series as it deals with only wakeup and not enumeration. The first part of the series deals with enumeration and the next part deals with wakeup. Updated commit text for wrapper driver patches. Added error checks in get_port_index and setup_irq call which were missing in v13. Added SOB and CDB tags appropriately for the patches. Rebased code on top of latest usb next. DT changes have been removed and will be sent as a separate series. Changes in v13: This series is a subset of patches in v11 as the first 3 patches in v11 have been mereged into usb-next. Moved dr_mode property from platform specific files to common sc8280xp DT. Fixed function call wrapping, added comments and replaced #defines with enum in dwc3-qcom for identifying IRQ index appropriately. Fixed nitpicks pointed out in v11 for suspend-resume handling. Added reported-by tag for phy refactoring patch as a compile error was found by kernel test bot [1]. Removed reviewed-by tag of maintainer for phy refactoring patch as a minor change of increasing phy-names array size by 2-bytes was done to fix compilation issue mentioned in [1]. Changes in v12: Pushed as a subset of acked but no-yet-merged patches of v11 with intent of making rebase of other patches easy. Active reviewers from community suggested that it would be better to push the whole series in one go as it would give good clarity and context for all the patches in the series. So pushed v13 for the same addressing comments received in v11. Changes in v11: Implemented port_count calculation by reading interrupt-names from DT. Refactored IRQ handling in dwc3-qcom. Moving of macros to xhci-ext-caps.h made as a separate patch. Names of interrupts to be displayed on /proc/interrupts set to the ones present in DT. Changes in v10: Refactored phy init/exit/power-on/off functions in dwc3 core Refactored dwc3-qcom irq registration and handling Implemented wakeup for multiport irq's Moved few macros from xhci.h to xhci-ext-caps.h Fixed nits pointed out in v9 Fixed Co-developed by and SOB tags in patches 5 and 11 Changes in v9: Added IRQ support for DP/DM/SS MP Irq's of SC8280 Refactored code to read port count by accessing xhci registers Changes in v8: Reorganised code in patch-5 Fixed nitpicks in code according to comments received on v7 Fixed indentation in DT patches Added drive strength for pinctrl nodes in SA8295 DT Changes in v7: Added power event irq's for Multiport controller. Udpated commit text for patch-9 (adding DT changes for enabling first port of multiport controller on sa8540-ride). Fixed check-patch warnings for driver code. Fixed DT binding errors for changes in snps,dwc3.yaml Reabsed code on top of usb-next Changes in v6: Updated comments in code after. Updated variables names appropriately as per review comments. Updated commit text in patch-2 and added additional info as per review comments. The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected it in this version. Changes in v5: Added DT support for first port of Teritiary USB controller on SA8540-Ride Added support for reading port info from XHCI Extended Params registers. Changes in RFC v4: Added DT support for SA8295p. Changes in RFC v3: Incase any PHY init fails, then clear/exit the PHYs that are already initialized. Changes in RFC v2: Changed dwc3_count_phys to return the number of PHY Phandles in the node. This will be used now in dwc3_extract_num_phys to increment num_usb2_phy and num_usb3_phy. Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its structure such that the first half is for HS-PHY and second half is for SS-PHY. In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is present, pass proper SS_IDX else pass -1. Tested enumeration interrupt registration on Tertiary controller of SA8295 ADP: / # lsusb Bus 001 Device 001: ID 1d6b:0002 Bus 002 Device 001: ID 1d6b:0003 Bus 001 Device 002: ID 046d:c06a / # / # dmesg | grep ports [ 0.066250] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 0.154668] dwc3 a400000.usb: K: hs-ports: 4 ss-ports: 2 [ 0.223137] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.1 Enhanced SuperSpeed [ 0.227795] hub 1-0:1.0: 4 ports detected [ 0.233724] hub 2-0:1.0: 2 ports detected Tested interrupt registration for all 4 ports of SA8295 ADP: / # cat /proc/interrupts |grep phy 162: 0 0 0 0 0 0 0 0 PDC 127 Edge dp_hs_phy_1 163: 0 0 0 0 0 0 0 0 PDC 129 Edge dp_hs_phy_2 164: 0 0 0 0 0 0 0 0 PDC 131 Edge dp_hs_phy_3 165: 0 0 0 0 0 0 0 0 PDC 133 Edge dp_hs_phy_4 166: 0 0 0 0 0 0 0 0 PDC 126 Edge dm_hs_phy_1 167: 0 0 0 0 0 0 0 0 PDC 16 Level ss_phy_1 168: 0 0 0 0 0 0 0 0 PDC 128 Edge dm_hs_phy_2 169: 0 0 0 0 0 0 0 0 PDC 17 Level ss_phy_2 170: 0 0 0 0 0 0 0 0 PDC 130 Edge dm_hs_phy_3 171: 0 0 0 0 0 0 0 0 PDC 132 Edge dm_hs_phy_4 173: 0 0 0 0 0 0 0 0 PDC 14 Edge dp_hs_phy_irq 174: 0 0 0 0 0 0 0 0 PDC 15 Edge dm_hs_phy_irq 175: 0 0 0 0 0 0 0 0 PDC 138 Level ss_phy_irq Tested working of ADB on SM8550 MTP. Links to previous versions: Link to v19: https://lore.kernel.org/all/20240404051229.3082902-1-quic_kriskura@quicinc.com/ Link to v18: https://lore.kernel.org/all/20240326113253.3010447-1-quic_kriskura@quicinc.com/ Link to v17: https://lore.kernel.org/all/20240326102809.2940123-1-quic_kriskura@quicinc.com/ Link to v16: https://lore.kernel.org/all/20240307062052.2319851-1-quic_kriskura@quicinc.com/ Link to v15: https://lore.kernel.org/all/20240216005756.762712-1-quic_kriskura@quicinc.com/ Link to v14: https://lore.kernel.org/all/20240206051825.1038685-1-quic_kriskura@quicinc.com/ Link to v13: https://lore.kernel.org/all/20231007154806.605-1-quic_kriskura@quicinc.com/ Link to v12: https://lore.kernel.org/all/20231004165922.25642-1-quic_kriskura@quicinc.com/ Link to v11: https://lore.kernel.org/all/20230828133033.11988-1-quic_kriskura@quicinc.com/ Link to v10: https://lore.kernel.org/all/20230727223307.8096-1-quic_kriskura@quicinc.com/ Link to v9: https://lore.kernel.org/all/20230621043628.21485-1-quic_kriskura@quicinc.com/ Link to v8: https://lore.kernel.org/all/20230514054917.21318-1-quic_kriskura@quicinc.com/ Link to v7: https://lore.kernel.org/all/20230501143445.3851-1-quic_kriskura@quicinc.com/ Link to v6: https://lore.kernel.org/all/20230405125759.4201-1-quic_kriskura@quicinc.com/ Link to v5: https://lore.kernel.org/all/20230310163420.7582-1-quic_kriskura@quicinc.com/ Link to RFC v4: https://lore.kernel.org/all/20230115114146.12628-1-quic_kriskura@quicinc.com/ Link to RFC v3: https://lore.kernel.org/all/1654709787-23686-1-git-send-email-quic_harshq@quicinc.com/#r Link to RFC v2: https://lore.kernel.org/all/1653560029-6937-1-git-send-email-quic_harshq@quicinc.com/#r Krishna Kurapati (9): dt-bindings: usb: Add bindings for multiport properties on DWC3 controller usb: dwc3: core: Access XHCI address space temporarily to read port info usb: dwc3: core: Skip setting event buffers for host only controllers usb: dwc3: core: Refactor PHY logic to support Multiport Controller dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport usb: dwc3: qcom: Add helper function to request wakeup interrupts usb: dwc3: qcom: Refactor IRQ handling in glue driver usb: dwc3: qcom: Enable wakeup for applicable ports of multiport usb: dwc3: qcom: Add multiport suspend/resume support for wrapper .../devicetree/bindings/usb/qcom,dwc3.yaml | 34 ++ .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +- drivers/usb/dwc3/core.c | 325 +++++++++++++----- drivers/usb/dwc3/core.h | 19 +- drivers/usb/dwc3/drd.c | 15 +- drivers/usb/dwc3/dwc3-qcom.c | 251 +++++++++----- 6 files changed, 482 insertions(+), 175 deletions(-)