| Message ID | 20240319115932.4108904-1-serghox@gmail.com |
|---|---|
| Headers | show |
| Series | mmc: sdhci-of-dwcmshc: Add CQE support | expand |
On 19/03/24 13:59, Sergey Khimich wrote: > From: Sergey Khimich <serghox@gmail.com> > > There are could be specific limitations for some mmc > controllers for setting cqhci transfer descriptors. > So add callback to allow implement driver specific function. > > Signed-off-by: Sergey Khimich <serghox@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> > --- > drivers/mmc/host/cqhci-core.c | 11 ++++++++--- > drivers/mmc/host/cqhci.h | 4 ++++ > 2 files changed, 12 insertions(+), 3 deletions(-) > > diff --git a/drivers/mmc/host/cqhci-core.c b/drivers/mmc/host/cqhci-core.c > index 41e94cd14109..c14d7251d0bb 100644 > --- a/drivers/mmc/host/cqhci-core.c > +++ b/drivers/mmc/host/cqhci-core.c > @@ -474,8 +474,8 @@ static int cqhci_dma_map(struct mmc_host *host, struct mmc_request *mrq) > return sg_count; > } > > -static void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end, > - bool dma64) > +void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end, > + bool dma64) > { > __le32 *attr = (__le32 __force *)desc; > > @@ -495,6 +495,7 @@ static void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end, > dataddr[0] = cpu_to_le32(addr); > } > } > +EXPORT_SYMBOL(cqhci_set_tran_desc); > > static int cqhci_prep_tran_desc(struct mmc_request *mrq, > struct cqhci_host *cq_host, int tag) > @@ -522,7 +523,11 @@ static int cqhci_prep_tran_desc(struct mmc_request *mrq, > > if ((i+1) == sg_count) > end = true; > - cqhci_set_tran_desc(desc, addr, len, end, dma64); > + if (cq_host->ops->set_tran_desc) > + cq_host->ops->set_tran_desc(cq_host, &desc, addr, len, end, dma64); > + else > + cqhci_set_tran_desc(desc, addr, len, end, dma64); > + > desc += cq_host->trans_desc_len; > } > > diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h > index 1a12e40a02e6..fab9d74445ba 100644 > --- a/drivers/mmc/host/cqhci.h > +++ b/drivers/mmc/host/cqhci.h > @@ -293,6 +293,9 @@ struct cqhci_host_ops { > int (*program_key)(struct cqhci_host *cq_host, > const union cqhci_crypto_cfg_entry *cfg, int slot); > #endif > + void (*set_tran_desc)(struct cqhci_host *cq_host, u8 **desc, > + dma_addr_t addr, int len, bool end, bool dma64); > + > }; > > static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg) > @@ -318,6 +321,7 @@ irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error, > int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64); > struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev); > int cqhci_deactivate(struct mmc_host *mmc); > +void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end, bool dma64); > static inline int cqhci_suspend(struct mmc_host *mmc) > { > return cqhci_deactivate(mmc);
On Tue, 19 Mar 2024 at 12:59, Sergey Khimich <serghox@gmail.com> wrote: > > Hello! > > This is implementation of SDHCI CQE support for sdhci-of-dwcmshc driver. > For enabling CQE support just set 'supports-cqe' in your DevTree file > for appropriate mmc node. > > Also, while implementing CQE support for the driver, I faced with a problem > which I will describe below. > According to the IP block documentation CQE works only with "AMDA-2 only" > mode which is activated only with v4 mode enabled. I see in dwcmshc_probe() > function that v4 mode gets enabled only for 'sdhci_dwcmshc_bf3_pdata' > platform data. > > So my question is: is it correct to enable v4 mode for all platform data > if 'SDHCI_CAN_64BIT_V4' bit is set in hw? > > Because I`m afraid that enabling v4 mode for some platforms could break > them down. On the other hand, if host controller says that it can do v4 > (caps & SDHCI_CAN_64BIT_V4), lets do v4 or disable it manualy by some > quirk. Anyway - RFC. > > > v2: > - Added dwcmshc specific cqe_disable hook to prevent losing > in-flight cmd when an ioctl is issued and cqe_disable is called; > > - Added processing 128Mb boundary for the host memory data buffer size > and the data buffer. For implementing this processing an extra > callback is added to the struct 'sdhci_ops'. > > - Fixed typo. > > v3: > - Fix warning reported by kernel test robot: > | Reported-by: kernel test robot <lkp@intel.com> > | Closes: https://lore.kernel.org/oe-kbuild-all/202309270807.VoVn81m6-lkp@intel.com/ > | Closes: https://lore.kernel.org/oe-kbuild-all/202309300806.dcR19kcE-lkp@intel.com/ > > v4: > - Data reset moved to custom driver tuning hook. > - Removed unnecessary dwcmshc_sdhci_cqe_disable() func > - Removed unnecessary dwcmshc_cqhci_set_tran_desc. Export and use > cqhci_set_tran_desc() instead. > - Provide a hook for cqhci_set_tran_desc() instead of cqhci_prep_tran_desc(). > - Fix typo: int_clok_disable --> int_clock_disable > > v5: > - Fix warning reported by kernel test robot: > | Reported-by: kernel test robot <lkp@intel.com> > | Closes: https://lore.kernel.org/oe-kbuild-all/202312301130.itEZhhI5-lkp@intel.com/ > > v6: > - Rebase to master branch > - Fix typo; > - Fix double blank line; > - Add cqhci_suspend() and cqhci_resume() functions > to support mmc suspend-to-ram (s2r); > - Move reading DWCMSHC_P_VENDOR_AREA2 register under "supports-cqe" > condition as not all IPs have that register; > - Remove sdhci V4 mode from the list of prerequisites to init cqhci. > > v7: > - Add disabling MMC_CAP2_CQE and MMC_CAP2_CQE_DCMD caps > in case of CQE init fails to prevent problems in suspend/resume > functions. > > Sergey Khimich (2): > mmc: cqhci: Add cqhci set_tran_desc() callback > mmc: sdhci-of-dwcmshc: Implement SDHCI CQE support > > drivers/mmc/host/Kconfig | 1 + > drivers/mmc/host/cqhci-core.c | 11 +- > drivers/mmc/host/cqhci.h | 4 + > drivers/mmc/host/sdhci-of-dwcmshc.c | 191 +++++++++++++++++++++++++++- > 4 files changed, 202 insertions(+), 5 deletions(-) > Applied for next and by fixing a minor conflict when applying, thanks! Kind regards Uffe
Hello! This is implementation of SDHCI CQE support for sdhci-of-dwcmshc driver. For enabling CQE support just set 'supports-cqe' in your DevTree file for appropriate mmc node. Also, while implementing CQE support for the driver, I faced with a problem which I will describe below. According to the IP block documentation CQE works only with "AMDA-2 only" mode which is activated only with v4 mode enabled. I see in dwcmshc_probe() function that v4 mode gets enabled only for 'sdhci_dwcmshc_bf3_pdata' platform data. So my question is: is it correct to enable v4 mode for all platform data if 'SDHCI_CAN_64BIT_V4' bit is set in hw? Because I`m afraid that enabling v4 mode for some platforms could break them down. On the other hand, if host controller says that it can do v4 (caps & SDHCI_CAN_64BIT_V4), lets do v4 or disable it manualy by some quirk. Anyway - RFC. v2: - Added dwcmshc specific cqe_disable hook to prevent losing in-flight cmd when an ioctl is issued and cqe_disable is called; - Added processing 128Mb boundary for the host memory data buffer size and the data buffer. For implementing this processing an extra callback is added to the struct 'sdhci_ops'. - Fixed typo. v3: - Fix warning reported by kernel test robot: | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202309270807.VoVn81m6-lkp@intel.com/ | Closes: https://lore.kernel.org/oe-kbuild-all/202309300806.dcR19kcE-lkp@intel.com/ v4: - Data reset moved to custom driver tuning hook. - Removed unnecessary dwcmshc_sdhci_cqe_disable() func - Removed unnecessary dwcmshc_cqhci_set_tran_desc. Export and use cqhci_set_tran_desc() instead. - Provide a hook for cqhci_set_tran_desc() instead of cqhci_prep_tran_desc(). - Fix typo: int_clok_disable --> int_clock_disable v5: - Fix warning reported by kernel test robot: | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202312301130.itEZhhI5-lkp@intel.com/ v6: - Rebase to master branch - Fix typo; - Fix double blank line; - Add cqhci_suspend() and cqhci_resume() functions to support mmc suspend-to-ram (s2r); - Move reading DWCMSHC_P_VENDOR_AREA2 register under "supports-cqe" condition as not all IPs have that register; - Remove sdhci V4 mode from the list of prerequisites to init cqhci. v7: - Add disabling MMC_CAP2_CQE and MMC_CAP2_CQE_DCMD caps in case of CQE init fails to prevent problems in suspend/resume functions. Sergey Khimich (2): mmc: cqhci: Add cqhci set_tran_desc() callback mmc: sdhci-of-dwcmshc: Implement SDHCI CQE support drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/cqhci-core.c | 11 +- drivers/mmc/host/cqhci.h | 4 + drivers/mmc/host/sdhci-of-dwcmshc.c | 191 +++++++++++++++++++++++++++- 4 files changed, 202 insertions(+), 5 deletions(-)