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[7/8] dt-bindings: clock: qcom: Add SM7150 VIDEOCC clocks

Message ID 20240220165240.154716-8-danila@jiaxyga.com
State Superseded
Headers show
Series Add dispcc, videocc and camcc for SM7150. | expand

Commit Message

Danila Tikhonov Feb. 20, 2024, 4:52 p.m. UTC 
Add device tree bindings for the video clock controller on Qualcomm
SM7150 platform.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 .../bindings/clock/qcom,sm7150-videocc.yaml   | 58 +++++++++++++++++++
 .../dt-bindings/clock/qcom,sm7150-videocc.h   | 28 +++++++++
 2 files changed, 86 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm7150-videocc.yaml
 create mode 100644 include/dt-bindings/clock/qcom,sm7150-videocc.h

Comments

Rob Herring (Arm) Feb. 23, 2024, 1:46 p.m. UTC | #1 
On Tue, 20 Feb 2024 19:52:39 +0300, Danila Tikhonov wrote:
> Add device tree bindings for the video clock controller on Qualcomm
> SM7150 platform.
> 
> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
> ---
>  .../bindings/clock/qcom,sm7150-videocc.yaml   | 58 +++++++++++++++++++
>  .../dt-bindings/clock/qcom,sm7150-videocc.h   | 28 +++++++++
>  2 files changed, 86 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm7150-videocc.yaml
>  create mode 100644 include/dt-bindings/clock/qcom,sm7150-videocc.h
> 

Reviewed-by: Rob Herring <robh@kernel.org>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm7150-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm7150-videocc.yaml
new file mode 100644
index 000000000000..037ffc71e70e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm7150-videocc.yaml
@@ -0,0 +1,58 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm7150-videocc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Video Clock & Reset Controller on SM7150
+
+maintainers:
+  - Danila Tikhonov <danila@jiaxyga.com>
+  - David Wronek <david@mainlining.org>
+  - Jens Reidel <adrian@travitia.xyz>
+
+description: |
+  Qualcomm video clock control module provides the clocks, resets and power
+  domains on SM7150.
+
+  See also:: include/dt-bindings/clock/qcom,videocc-sm7150.h
+
+properties:
+  compatible:
+    const: qcom,sm7150-videocc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Board Always On XO source
+
+  power-domains:
+    maxItems: 1
+    description:
+      CX power domain.
+
+required:
+  - compatible
+  - clocks
+  - power-domains
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+    videocc: clock-controller@ab00000 {
+      compatible = "qcom,sm7150-videocc";
+      reg = <0x0ab00000 0x10000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>;
+      power-domains = <&rpmhpd RPMHPD_CX>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
diff --git a/include/dt-bindings/clock/qcom,sm7150-videocc.h b/include/dt-bindings/clock/qcom,sm7150-videocc.h
new file mode 100644
index 000000000000..ac30b3d45496
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm7150-videocc.h
@@ -0,0 +1,28 @@ 
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM7150_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM7150_H
+
+#define VIDEO_PLL0			0
+#define VIDEO_CC_IRIS_AHB_CLK		1
+#define VIDEO_CC_IRIS_CLK_SRC		2
+#define VIDEO_CC_MVS0_AXI_CLK		3
+#define VIDEO_CC_MVS0_CORE_CLK		4
+#define VIDEO_CC_MVS1_AXI_CLK		5
+#define VIDEO_CC_MVS1_CORE_CLK		6
+#define VIDEO_CC_MVSC_CORE_CLK		7
+#define VIDEO_CC_MVSC_CTL_AXI_CLK	8
+#define VIDEO_CC_VENUS_AHB_CLK		9
+#define VIDEO_CC_XO_CLK			10
+#define VIDEO_CC_XO_CLK_SRC		11
+
+/* VIDEO_CC GDSCRs */
+#define VENUS_GDSC			0
+#define VCODEC0_GDSC			1
+#define VCODEC1_GDSC			2
+
+#endif