| Message ID | 20240220-fd-sc7180-explicit-ubwc-v1-1-611a58091724@linaro.org |
|---|---|
| State | Accepted |
| Commit | 0d7dfc79fb9b4b81f642f84796111f2bae8427e2 |
| Headers | show |
| Series | drm/msm/a6xx: specify UBWC config for sc7180 | expand |
On Tue, Feb 20, 2024 at 5:12 PM Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > Historically the Adreno driver has not been updating memory > configuration registers on a618 (SC7180 platform) implying that the > default configuration is fine. After the rework performed in the commit > 8814455a0e54 ("drm/msm: Refactor UBWC config setting") the function > a6xx_calc_ubwc_config() still contained this shortcut and did not > calculate UBWC configuration. However the function which now actually > updates hardware registers, a6xx_set_ubwc_config(), doesn't contain such > check. > > Rather than adding the check to a6xx_set_ubwc_config(), fill in the > UBWC config for a618 (based on readings from SC7180). > > Reported-by: Leonard Lausen <leonard@lausen.nl> > Link: https://gitlab.freedesktop.org/drm/msm/-/issues/49 > Fixes: 8814455a0e54 ("drm/msm: Refactor UBWC config setting") > Cc: Connor Abbott <cwabbott0@gmail.com> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Thanks! Reviewed-by: Connor Abbott <cwabbott0@gmail.com> > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index c9c55e2ea584..dc80e5940f51 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1292,9 +1292,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) > gpu->ubwc_config.ubwc_mode = 1; > } > > - /* a618 is using the hw default values */ > if (adreno_is_a618(gpu)) > - return; > + gpu->ubwc_config.highest_bank_bit = 14; > > if (adreno_is_a619_holi(gpu)) > gpu->ubwc_config.highest_bank_bit = 13; > > --- > base-commit: 41c177cf354126a22443b5c80cec9fdd313e67e1 > change-id: 20240220-fd-sc7180-explicit-ubwc-40953fa55947 > > Best regards, > -- > Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c9c55e2ea584..dc80e5940f51 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1292,9 +1292,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.ubwc_mode = 1; } - /* a618 is using the hw default values */ if (adreno_is_a618(gpu)) - return; + gpu->ubwc_config.highest_bank_bit = 14; if (adreno_is_a619_holi(gpu)) gpu->ubwc_config.highest_bank_bit = 13;
Historically the Adreno driver has not been updating memory configuration registers on a618 (SC7180 platform) implying that the default configuration is fine. After the rework performed in the commit 8814455a0e54 ("drm/msm: Refactor UBWC config setting") the function a6xx_calc_ubwc_config() still contained this shortcut and did not calculate UBWC configuration. However the function which now actually updates hardware registers, a6xx_set_ubwc_config(), doesn't contain such check. Rather than adding the check to a6xx_set_ubwc_config(), fill in the UBWC config for a618 (based on readings from SC7180). Reported-by: Leonard Lausen <leonard@lausen.nl> Link: https://gitlab.freedesktop.org/drm/msm/-/issues/49 Fixes: 8814455a0e54 ("drm/msm: Refactor UBWC config setting") Cc: Connor Abbott <cwabbott0@gmail.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) --- base-commit: 41c177cf354126a22443b5c80cec9fdd313e67e1 change-id: 20240220-fd-sc7180-explicit-ubwc-40953fa55947 Best regards,