| Message ID | 20240206085238.1208256-5-tudor.ambarus@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | spi: s3c64xx: add support for google,gs101-spi | expand |
Hi Tudor, On Tue, 6 Feb 2024 at 08:52, Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > Add support for GS101 SPI. GS101 integrates 16 SPI nodes, all with 64 > bytes FIFOs. GS101 allows just 32 bit register accesses, otherwise a > Serror Interrupt is raised. Do the write reg accesses in 32 bits. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- The patch ordering seems a bit off with this series..I believe it should be 1) dt-bindings patch (docs first) 2) Add the use_32bit_io flag / functionality 3) gs101 support (this patch) that uses the use_32bit_io functionality Peter. > drivers/spi/spi-s3c64xx.c | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c > index cb45ad615f3d..9ad0d513fb30 100644 > --- a/drivers/spi/spi-s3c64xx.c > +++ b/drivers/spi/spi-s3c64xx.c > @@ -19,7 +19,7 @@ > #include <linux/spi/spi.h> > #include <linux/types.h> > > -#define MAX_SPI_PORTS 12 > +#define MAX_SPI_PORTS 16 > #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) > #define AUTOSUSPEND_TIMEOUT 2000 > > @@ -1538,6 +1538,19 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { > .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, > }; > > +static const struct s3c64xx_spi_port_config gs101_spi_port_config = { > + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, > + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, > + .rx_lvl_offset = 15, > + .tx_st_done = 25, > + .clk_div = 4, > + .high_speed = true, > + .clk_from_cmu = true, > + .has_loopback = true, > + .use_32bit_io = true, > + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, > +}; > + > static const struct platform_device_id s3c64xx_spi_driver_ids[] = { > { > .name = "s3c2443-spi", > @@ -1550,6 +1563,9 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = { > }; > > static const struct of_device_id s3c64xx_spi_dt_match[] = { > + { .compatible = "google,gs101-spi", > + .data = &gs101_spi_port_config, > + }, > { .compatible = "samsung,s3c2443-spi", > .data = &s3c2443_spi_port_config, > }, > -- > 2.43.0.594.gd9cf4e227d-goog >
On Tue, Feb 06, 2024 at 10:12:30AM +0000, Peter Griffin wrote: > The patch ordering seems a bit off with this series..I believe it should be > 1) dt-bindings patch (docs first) > 2) Add the use_32bit_io flag / functionality > 3) gs101 support (this patch) that uses the use_32bit_io functionality That's the ordering the series has? There's a random cleanup patch tacked on the front but that really ought to be separate anyway.
On Tue, 6 Feb 2024 at 11:19, Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > > > On 2/6/24 11:04, Mark Brown wrote: > > On Tue, Feb 06, 2024 at 10:12:30AM +0000, Peter Griffin wrote: > > > >> The patch ordering seems a bit off with this series..I believe it should be > >> 1) dt-bindings patch (docs first) > >> 2) Add the use_32bit_io flag / functionality > >> 3) gs101 support (this patch) that uses the use_32bit_io functionality > > > > That's the ordering the series has? There's a random cleanup patch > > tacked on the front but that really ought to be separate anyway. > > I put the include <linux/types.h> patch first because I considered it a > fix (driver is using u32) and because I need types.h in patch 3/4. Fixes > first, then bindings, then driver. > > Was I wrong? No my mistake, sorry for the noise. Gmail showed this driver change as the first patch after the cover letter but the subject was hidden so it wasn't obvious it was [4/4]
On Tue, Feb 6, 2024 at 2:52 AM Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > Add support for GS101 SPI. GS101 integrates 16 SPI nodes, all with 64 > bytes FIFOs. GS101 allows just 32 bit register accesses, otherwise a > Serror Interrupt is raised. Do the write reg accesses in 32 bits. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > drivers/spi/spi-s3c64xx.c | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c > index cb45ad615f3d..9ad0d513fb30 100644 > --- a/drivers/spi/spi-s3c64xx.c > +++ b/drivers/spi/spi-s3c64xx.c > @@ -19,7 +19,7 @@ > #include <linux/spi/spi.h> > #include <linux/types.h> > > -#define MAX_SPI_PORTS 12 > +#define MAX_SPI_PORTS 16 > #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) > #define AUTOSUSPEND_TIMEOUT 2000 > > @@ -1538,6 +1538,19 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { > .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, > }; > > +static const struct s3c64xx_spi_port_config gs101_spi_port_config = { > + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, > + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, > + .rx_lvl_offset = 15, > + .tx_st_done = 25, > + .clk_div = 4, > + .high_speed = true, > + .clk_from_cmu = true, > + .has_loopback = true, > + .use_32bit_io = true, > + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, > +}; > + > static const struct platform_device_id s3c64xx_spi_driver_ids[] = { > { > .name = "s3c2443-spi", > @@ -1550,6 +1563,9 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = { > }; > > static const struct of_device_id s3c64xx_spi_dt_match[] = { > + { .compatible = "google,gs101-spi", > + .data = &gs101_spi_port_config, > + }, > { .compatible = "samsung,s3c2443-spi", > .data = &s3c2443_spi_port_config, > }, > -- > 2.43.0.594.gd9cf4e227d-goog >
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index cb45ad615f3d..9ad0d513fb30 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -19,7 +19,7 @@ #include <linux/spi/spi.h> #include <linux/types.h> -#define MAX_SPI_PORTS 12 +#define MAX_SPI_PORTS 16 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) #define AUTOSUSPEND_TIMEOUT 2000 @@ -1538,6 +1538,19 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, }; +static const struct s3c64xx_spi_port_config gs101_spi_port_config = { + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .clk_div = 4, + .high_speed = true, + .clk_from_cmu = true, + .has_loopback = true, + .use_32bit_io = true, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct platform_device_id s3c64xx_spi_driver_ids[] = { { .name = "s3c2443-spi", @@ -1550,6 +1563,9 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = { }; static const struct of_device_id s3c64xx_spi_dt_match[] = { + { .compatible = "google,gs101-spi", + .data = &gs101_spi_port_config, + }, { .compatible = "samsung,s3c2443-spi", .data = &s3c2443_spi_port_config, },
Add support for GS101 SPI. GS101 integrates 16 SPI nodes, all with 64 bytes FIFOs. GS101 allows just 32 bit register accesses, otherwise a Serror Interrupt is raised. Do the write reg accesses in 32 bits. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- drivers/spi/spi-s3c64xx.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)