| Message ID | 20231103173841.33651-1-richard.henderson@linaro.org |
|---|---|
| Headers | show |
| Series | target/sparc: floating-point cleanup | expand |
On 11/4/23 03:38, Richard Henderson wrote: > Major changes: > > (1) Get rid of the env->qt[01] temporaries and use TCGv_i128 for float128. > (2) Perform ieee exception check within the helpers, before any writeback > to the floating point registers. > (3) Split env->fsr into pieces to simplify update, especially compares. > > > r~ > > > Based-on: 20231101041132.174501-1-richard.henderson@linaro.org > ("[PATCH v2 00/21] target/sparc: Cleanup condition codes etc") Ping. Prerequisites are upstream, and it rebases cleanly on master. For reference, https://gitlab.com/rth7680/qemu/-/commits/tgt-sparc-fp r~ > > > Richard Henderson (22): > target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for ASI_M_BCOPY > target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for ASI_M_BFILL > target/sparc: Remove gen_dest_fpr_F > target/sparc: Introduce gen_{load,store}_fpr_Q > target/sparc: Inline FNEG, FABS > target/sparc: Use i128 for FSQRTq > target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq > target/sparc: Use i128 for FqTOs, FqTOi > target/sparc: Use i128 for FqTOd, FqTOx > target/sparc: Use i128 for FCMPq, FCMPEq > target/sparc: Use i128 for FsTOq, FiTOq > target/sparc: Use i128 for FdTOq, FxTOq > target/sparc: Use i128 for Fdmulq > target/sparc: Remove qt0, qt1 temporaries > target/sparc: Introduce cpu_get_fsr, cpu_put_fsr > target/split: Split ver from env->fsr > target/sparc: Clear cexc and ftt in do_check_ieee_exceptions > target/sparc: Merge check_ieee_exceptions with FPop helpers > target/sparc: Split cexc and ftt from env->fsr > target/sparc: Remove cpu_fsr > target/sparc: Split fcc out of env->fsr > target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK > > target/sparc/cpu.h | 39 +- > target/sparc/helper.h | 116 ++---- > linux-user/sparc/cpu_loop.c | 2 +- > linux-user/sparc/signal.c | 14 +- > target/sparc/cpu.c | 32 +- > target/sparc/fop_helper.c | 510 +++++++++++++---------- > target/sparc/gdbstub.c | 8 +- > target/sparc/ldst_helper.c | 3 - > target/sparc/machine.c | 38 +- > target/sparc/translate.c | 799 ++++++++++++------------------------ > 10 files changed, 680 insertions(+), 881 deletions(-) >
On 28/01/2024 06:49, Richard Henderson wrote: > On 11/4/23 03:38, Richard Henderson wrote: >> Major changes: >> >> (1) Get rid of the env->qt[01] temporaries and use TCGv_i128 for float128. >> (2) Perform ieee exception check within the helpers, before any writeback >> to the floating point registers. >> (3) Split env->fsr into pieces to simplify update, especially compares. >> >> >> r~ >> >> >> Based-on: 20231101041132.174501-1-richard.henderson@linaro.org >> ("[PATCH v2 00/21] target/sparc: Cleanup condition codes etc") > > Ping. > > Prerequisites are upstream, and it rebases cleanly on master. > For reference, > > https://gitlab.com/rth7680/qemu/-/commits/tgt-sparc-fp > > r~ Oops looks like I forgot about this series. I'm not sure I have any images that explicitly test floating point operations, but I can at least run it through my OpenBIOS test images and check for regressions over the next couple of days. >> Richard Henderson (22): >> target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for ASI_M_BCOPY >> target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for ASI_M_BFILL >> target/sparc: Remove gen_dest_fpr_F >> target/sparc: Introduce gen_{load,store}_fpr_Q >> target/sparc: Inline FNEG, FABS >> target/sparc: Use i128 for FSQRTq >> target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq >> target/sparc: Use i128 for FqTOs, FqTOi >> target/sparc: Use i128 for FqTOd, FqTOx >> target/sparc: Use i128 for FCMPq, FCMPEq >> target/sparc: Use i128 for FsTOq, FiTOq >> target/sparc: Use i128 for FdTOq, FxTOq >> target/sparc: Use i128 for Fdmulq >> target/sparc: Remove qt0, qt1 temporaries >> target/sparc: Introduce cpu_get_fsr, cpu_put_fsr >> target/split: Split ver from env->fsr >> target/sparc: Clear cexc and ftt in do_check_ieee_exceptions >> target/sparc: Merge check_ieee_exceptions with FPop helpers >> target/sparc: Split cexc and ftt from env->fsr >> target/sparc: Remove cpu_fsr >> target/sparc: Split fcc out of env->fsr >> target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK >> >> target/sparc/cpu.h | 39 +- >> target/sparc/helper.h | 116 ++---- >> linux-user/sparc/cpu_loop.c | 2 +- >> linux-user/sparc/signal.c | 14 +- >> target/sparc/cpu.c | 32 +- >> target/sparc/fop_helper.c | 510 +++++++++++++---------- >> target/sparc/gdbstub.c | 8 +- >> target/sparc/ldst_helper.c | 3 - >> target/sparc/machine.c | 38 +- >> target/sparc/translate.c | 799 ++++++++++++------------------------ >> 10 files changed, 680 insertions(+), 881 deletions(-) ATB, Mark.
On 28/01/2024 06:49, Richard Henderson wrote: > On 11/4/23 03:38, Richard Henderson wrote: >> Major changes: >> >> (1) Get rid of the env->qt[01] temporaries and use TCGv_i128 for float128. >> (2) Perform ieee exception check within the helpers, before any writeback >> to the floating point registers. >> (3) Split env->fsr into pieces to simplify update, especially compares. >> >> >> r~ >> >> >> Based-on: 20231101041132.174501-1-richard.henderson@linaro.org >> ("[PATCH v2 00/21] target/sparc: Cleanup condition codes etc") > > Ping. > > Prerequisites are upstream, and it rebases cleanly on master. > For reference, > > https://gitlab.com/rth7680/qemu/-/commits/tgt-sparc-fp > > > r~ I've tested the above branch on my SPARC32 and SPARC64 images, and whilst I don't think they particularly exercise FP instructions, I don't see any regressions so: Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> I'm happy for you to take this via tcg-next if that's easiest for you. >> Richard Henderson (22): >> target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for ASI_M_BCOPY >> target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for ASI_M_BFILL >> target/sparc: Remove gen_dest_fpr_F >> target/sparc: Introduce gen_{load,store}_fpr_Q >> target/sparc: Inline FNEG, FABS >> target/sparc: Use i128 for FSQRTq >> target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq >> target/sparc: Use i128 for FqTOs, FqTOi >> target/sparc: Use i128 for FqTOd, FqTOx >> target/sparc: Use i128 for FCMPq, FCMPEq >> target/sparc: Use i128 for FsTOq, FiTOq >> target/sparc: Use i128 for FdTOq, FxTOq >> target/sparc: Use i128 for Fdmulq >> target/sparc: Remove qt0, qt1 temporaries >> target/sparc: Introduce cpu_get_fsr, cpu_put_fsr >> target/split: Split ver from env->fsr >> target/sparc: Clear cexc and ftt in do_check_ieee_exceptions >> target/sparc: Merge check_ieee_exceptions with FPop helpers >> target/sparc: Split cexc and ftt from env->fsr >> target/sparc: Remove cpu_fsr >> target/sparc: Split fcc out of env->fsr >> target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK >> >> target/sparc/cpu.h | 39 +- >> target/sparc/helper.h | 116 ++---- >> linux-user/sparc/cpu_loop.c | 2 +- >> linux-user/sparc/signal.c | 14 +- >> target/sparc/cpu.c | 32 +- >> target/sparc/fop_helper.c | 510 +++++++++++++---------- >> target/sparc/gdbstub.c | 8 +- >> target/sparc/ldst_helper.c | 3 - >> target/sparc/machine.c | 38 +- >> target/sparc/translate.c | 799 ++++++++++++------------------------ >> 10 files changed, 680 insertions(+), 881 deletions(-) ATB, Mark.
On 2/1/24 07:49, Mark Cave-Ayland wrote:
> I'm happy for you to take this via tcg-next if that's easiest for you.
Yes, I can do that.
r~
Major changes: (1) Get rid of the env->qt[01] temporaries and use TCGv_i128 for float128. (2) Perform ieee exception check within the helpers, before any writeback to the floating point registers. (3) Split env->fsr into pieces to simplify update, especially compares. r~ Based-on: 20231101041132.174501-1-richard.henderson@linaro.org ("[PATCH v2 00/21] target/sparc: Cleanup condition codes etc") Richard Henderson (22): target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for ASI_M_BCOPY target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for ASI_M_BFILL target/sparc: Remove gen_dest_fpr_F target/sparc: Introduce gen_{load,store}_fpr_Q target/sparc: Inline FNEG, FABS target/sparc: Use i128 for FSQRTq target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq target/sparc: Use i128 for FqTOs, FqTOi target/sparc: Use i128 for FqTOd, FqTOx target/sparc: Use i128 for FCMPq, FCMPEq target/sparc: Use i128 for FsTOq, FiTOq target/sparc: Use i128 for FdTOq, FxTOq target/sparc: Use i128 for Fdmulq target/sparc: Remove qt0, qt1 temporaries target/sparc: Introduce cpu_get_fsr, cpu_put_fsr target/split: Split ver from env->fsr target/sparc: Clear cexc and ftt in do_check_ieee_exceptions target/sparc: Merge check_ieee_exceptions with FPop helpers target/sparc: Split cexc and ftt from env->fsr target/sparc: Remove cpu_fsr target/sparc: Split fcc out of env->fsr target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK target/sparc/cpu.h | 39 +- target/sparc/helper.h | 116 ++---- linux-user/sparc/cpu_loop.c | 2 +- linux-user/sparc/signal.c | 14 +- target/sparc/cpu.c | 32 +- target/sparc/fop_helper.c | 510 +++++++++++++---------- target/sparc/gdbstub.c | 8 +- target/sparc/ldst_helper.c | 3 - target/sparc/machine.c | 38 +- target/sparc/translate.c | 799 ++++++++++++------------------------ 10 files changed, 680 insertions(+), 881 deletions(-)