| Message ID | 20240103173349.398526-24-alex.bennee@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | testing and plugin updates for 9.0 (pre-PR) | expand |
Alex Bennée <alex.bennee@linaro.org> writes: > From: Akihiko Odaki <akihiko.odaki@daynix.com> > > It is initialized with a simple assignment and there is little room for > error. In fact, the validation is even more complex. > > Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> > Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Acked-by: Alistair Francis <alistair.francis@wdc.com> > Message-Id: <20231213-riscv-v7-2-a760156a337f@daynix.com> > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> ping: along with this are the RiscV maintainers happy for me to take: [PATCH v2 23/43] target/riscv: Remove misa_mxl validation [PATCH v2 24/43] target/riscv: Move misa_mxl_max to class [PATCH v2 25/43] target/riscv: Validate misa_mxl_max only once through my next pull request? <snip>
On Tue, Jan 9, 2024 at 1:43 AM Alex Bennée <alex.bennee@linaro.org> wrote: > > Alex Bennée <alex.bennee@linaro.org> writes: > > > From: Akihiko Odaki <akihiko.odaki@daynix.com> > > > > It is initialized with a simple assignment and there is little room for > > error. In fact, the validation is even more complex. > > > > Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> > > Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> > > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > > Acked-by: Alistair Francis <alistair.francis@wdc.com> > > Message-Id: <20231213-riscv-v7-2-a760156a337f@daynix.com> > > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> > > ping: along with this are the RiscV maintainers happy for me to take: > > [PATCH v2 23/43] target/riscv: Remove misa_mxl validation > [PATCH v2 24/43] target/riscv: Move misa_mxl_max to class > [PATCH v2 25/43] target/riscv: Validate misa_mxl_max only once > > through my next pull request? Yep! Go for it Alistair > > <snip> > > -- > Alex Bennée > Virtualisation Tech Lead @ Linaro >
Alistair Francis <alistair23@gmail.com> writes: > On Tue, Jan 9, 2024 at 1:43 AM Alex Bennée <alex.bennee@linaro.org> wrote: >> >> Alex Bennée <alex.bennee@linaro.org> writes: >> >> > From: Akihiko Odaki <akihiko.odaki@daynix.com> >> > >> > It is initialized with a simple assignment and there is little room for >> > error. In fact, the validation is even more complex. >> > >> > Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> >> > Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> >> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> >> > Acked-by: Alistair Francis <alistair.francis@wdc.com> >> > Message-Id: <20231213-riscv-v7-2-a760156a337f@daynix.com> >> > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> >> >> ping: along with this are the RiscV maintainers happy for me to take: >> >> [PATCH v2 23/43] target/riscv: Remove misa_mxl validation >> [PATCH v2 24/43] target/riscv: Move misa_mxl_max to class >> [PATCH v2 25/43] target/riscv: Validate misa_mxl_max only once >> >> through my next pull request? > > Yep! Go for it Sadly some of the recent changes that went through have created a merge conflict. Akihiko, Any chance you could re-spin just the MISA_MXL patches? > > Alistair > >> >> <snip> >> >> -- >> Alex Bennée >> Virtualisation Tech Lead @ Linaro >>
Alex Bennée <alex.bennee@linaro.org> writes: > Alistair Francis <alistair23@gmail.com> writes: > >> On Tue, Jan 9, 2024 at 1:43 AM Alex Bennée <alex.bennee@linaro.org> wrote: >>> >>> Alex Bennée <alex.bennee@linaro.org> writes: >>> >>> > From: Akihiko Odaki <akihiko.odaki@daynix.com> >>> > >>> > It is initialized with a simple assignment and there is little room for >>> > error. In fact, the validation is even more complex. >>> > >>> > Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> >>> > Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> >>> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> >>> > Acked-by: Alistair Francis <alistair.francis@wdc.com> >>> > Message-Id: <20231213-riscv-v7-2-a760156a337f@daynix.com> >>> > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> >>> >>> ping: along with this are the RiscV maintainers happy for me to take: >>> >>> [PATCH v2 23/43] target/riscv: Remove misa_mxl validation >>> [PATCH v2 24/43] target/riscv: Move misa_mxl_max to class >>> [PATCH v2 25/43] target/riscv: Validate misa_mxl_max only once >>> >>> through my next pull request? >> >> Yep! Go for it > > Sadly some of the recent changes that went through have created a merge > conflict. > > Akihiko, > > Any chance you could re-spin just the MISA_MXL patches? Never mind, I think I got it figured out.
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8a35683a345..ee17f65afb6 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -148,7 +148,7 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) } } -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) { RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); CPUClass *cc = CPU_CLASS(mcc); @@ -168,11 +168,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) default: g_assert_not_reached(); } - - if (env->misa_mxl_max != env->misa_mxl) { - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); - return; - } } static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) @@ -673,7 +668,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) static bool tcg_cpu_realize(CPUState *cs, Error **errp) { RISCVCPU *cpu = RISCV_CPU(cs); - Error *local_err = NULL; if (!riscv_cpu_tcg_compatible(cpu)) { g_autofree char *name = riscv_cpu_get_name(cpu); @@ -682,14 +676,11 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp) return false; } - riscv_cpu_validate_misa_mxl(cpu, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return false; - } + riscv_cpu_validate_misa_mxl(cpu); #ifndef CONFIG_USER_ONLY CPURISCVState *env = &cpu->env; + Error *local_err = NULL; CPU(cs)->tcg_cflags |= CF_PCREL;