| Message ID | 20240111-sm8150-dfs-support-v2-3-6edb44c83d3b@quicinc.com |
|---|---|
| State | Accepted |
| Commit | c8bf3e08c62533430a83d96d31d34c781483283c |
| Headers | show |
| Series | [v2,1/3] clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS on SM8150 | expand |
On 11.01.2024 07:32, Satya Priya Kakitapalli wrote: > Add gcc video axic, axi0 and axi1 resets for the global clock > controller on sm8150. > > Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> > --- Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index 80315307dbb4..a47ef9dfa808 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -3778,6 +3778,9 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = { [GCC_USB30_PRIM_BCR] = { 0xf000 }, [GCC_USB30_SEC_BCR] = { 0x10000 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, + [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 }, + [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 }, + [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 }, }; static struct gdsc *gcc_sm8150_gdscs[] = {
Add gcc video axic, axi0 and axi1 resets for the global clock controller on sm8150. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> --- drivers/clk/qcom/gcc-sm8150.c | 3 +++ 1 file changed, 3 insertions(+)