| Message ID | 20240109125814.3691033-7-tudor.ambarus@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | GS101 Oriole: CMU_PERIC0 support and USI updates | expand |
On 09/01/2024 13:58, Tudor Ambarus wrote: > The entire bus (PERIC) on which the GS101 serial resides only allows > 32-bit register accesses. The reg-io-width dt property is disallowed > for the "google,gs101-uart" compatible and instead the iotype is > inferred from the compatible. Always set UPIO_MEM32 iotype for the > gs101 earlycon. > > Reviewed-by: Peter Griffin <peter.griffin@linaro.org> > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- > v3: collect Peter's R-b tag > v2: update commit message > > drivers/tty/serial/samsung_tty.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index a81b61953a28..fed50423b7c1 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2812,6 +2812,17 @@ OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart", s5pv210_early_console_setup); +static int __init gs101_early_console_setup(struct earlycon_device *device, + const char *opt) +{ + /* gs101 always expects MMIO32 register accesses. */ + device->port.iotype = UPIO_MEM32; + + return s5pv210_early_console_setup(device, opt); +} + +OF_EARLYCON_DECLARE(gs101, "google,gs101-uart", gs101_early_console_setup); + /* Apple S5L */ static int __init apple_s5l_early_console_setup(struct earlycon_device *device, const char *opt)