| Message ID | 20240105-sm6350-qce-v1-2-416e5c7319ac@fairphone.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add Crypto Engine support for SM6350 | expand |
On Fri, Jan 05, 2024 at 05:15:44PM +0100, Luca Weiss wrote: > Add crypto engine (CE) and CE BAM related nodes and definitions for this > SoC. > > For reference: > > [ 2.297419] qcrypto 1dfa000.crypto: Crypto device found, version 5.5.1 > > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > --- > arch/arm64/boot/dts/qcom/sm6350.dtsi | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index 8fd6f4d03490..516aadbb16bb 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -1212,6 +1212,37 @@ ufs_mem_phy_lanes: phy@1d87400 { > }; > }; > > + cryptobam: dma-controller@1dc4000 { > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > + reg = <0 0x01dc4000 0 0x24000>; > + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; > + #dma-cells = <1>; > + qcom,ee = <0>; > + qcom,controlled-remotely; > + num-channels = <16>; > + qcom,num-ees = <4>; > + iommus = <&apps_smmu 0x432 0x0000>, > + <&apps_smmu 0x438 0x0001>, > + <&apps_smmu 0x43f 0x0000>, > + <&apps_smmu 0x426 0x0011>, > + <&apps_smmu 0x436 0x0011>; The last two lines look equivalent to me: 0x436 & ~0x0011 = 0x426. It's also a bit weird that the mask has one more digit than the stream ID. And ordered numerically (by stream ID, first number) it would be a bit easier to read. :-) Thanks, Stephan
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 8fd6f4d03490..516aadbb16bb 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1212,6 +1212,37 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <16>; + qcom,num-ees = <4>; + iommus = <&apps_smmu 0x432 0x0000>, + <&apps_smmu 0x438 0x0001>, + <&apps_smmu 0x43f 0x0000>, + <&apps_smmu 0x426 0x0011>, + <&apps_smmu 0x436 0x0011>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x432 0x0000>, + <&apps_smmu 0x438 0x0001>, + <&apps_smmu 0x43f 0x0000>, + <&apps_smmu 0x426 0x0011>, + <&apps_smmu 0x436 0x0011>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + ipa: ipa@1e40000 { compatible = "qcom,sm6350-ipa";
Add crypto engine (CE) and CE BAM related nodes and definitions for this SoC. For reference: [ 2.297419] qcrypto 1dfa000.crypto: Crypto device found, version 5.5.1 Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)