mbox series

[00/10] Add PCIe support for Qualcomm IPQ5332

Message ID 20231214062847.2215542-1-quic_ipkumar@quicinc.com
Headers show
Series Add PCIe support for Qualcomm IPQ5332 | expand

Message

Praveenkumar I Dec. 14, 2023, 6:28 a.m. UTC 
Patch series adds support for enabling the PCIe controller and
UNIPHY found on Qualcomm IPQ5332 platform. PCIe0 is Gen3 X1 and
PCIe1 is Gen3 X2 are added.

UNIPHY changes depends on
https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/
PCIe driver change depends on
https://lore.kernel.org/all/20230519090219.15925-1-quic_devipriy@quicinc.com/

Praveenkumar I (10):
  dt-bindings: clock: Add separate clocks for PCIe and USB for Combo PHY
  clk: qcom: ipq5332: Add separate clocks for PCIe and USB for Combo PHY
  arm64: dts: qcom: ipq5332: Add separate entry for USB pipe clock
  phy: qcom: Add support for Pipe clock rate from device data
  dt-bindings: phy: qcom,uniphy-pcie: Add ipq5332 bindings
  phy: qcom: ipq5332: Add support for g3x1 and g3x2 PCIe PHYs
  dt-bindings: PCI: qcom: Add IPQ5332 SoC
  pci: qcom: Add support for IPQ5332
  arm64: dts: qcom: ipq5332: Add PCIe related nodes
  arm64: dts: qcom: ipq5332: Enable PCIe phys and controllers

 .../bindings/clock/qcom,ipq5332-gcc.yaml      |   6 +-
 .../devicetree/bindings/pci/qcom,pcie.yaml    |  36 ++++
 .../bindings/phy/qcom,uniphy-pcie-28lp.yaml   |  65 +++++-
 arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts   |  74 +++++++
 arch/arm64/boot/dts/qcom/ipq5332.dtsi         | 188 +++++++++++++++++-
 drivers/clk/qcom/gcc-ipq5332.c                |   7 +-
 drivers/pci/controller/dwc/pcie-qcom.c        |   1 +
 .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c  |  49 ++++-
 8 files changed, 412 insertions(+), 14 deletions(-)

Comments

Praveenkumar I Dec. 15, 2023, 5:52 a.m. UTC | #1 
On 12/14/2023 12:45 PM, Dmitry Baryshkov wrote:
> On Thu, 14 Dec 2023 at 08:30, Praveenkumar I <quic_ipkumar@quicinc.com> wrote:
>> Add support for the PCIe controller on the Qualcomm
>> IPQ5332 SoC to the bindings.
>>
>> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
>> ---
>>   .../devicetree/bindings/pci/qcom,pcie.yaml    | 36 +++++++++++++++++++
>>   1 file changed, 36 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> index eadba38171e1..af5e67d2a984 100644
>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> @@ -21,6 +21,7 @@ properties:
>>             - qcom,pcie-apq8064
>>             - qcom,pcie-apq8084
>>             - qcom,pcie-ipq4019
>> +          - qcom,pcie-ipq5332
>>             - qcom,pcie-ipq6018
>>             - qcom,pcie-ipq8064
>>             - qcom,pcie-ipq8064-v2
>> @@ -170,6 +171,7 @@ allOf:
>>           compatible:
>>             contains:
>>               enum:
>> +              - qcom,pcie-ipq5332
>>                 - qcom,pcie-ipq6018
>>                 - qcom,pcie-ipq8074-gen3
>>       then:
>> @@ -332,6 +334,39 @@ allOf:
>>               - const: ahb # AHB reset
>>               - const: phy_ahb # PHY AHB reset
>>
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            enum:
>> +              - qcom,pcie-ipq5332
> As you seem to be depending on the ipq9574, could you please reuse the
> DT entry too?
Sure, will reuse ipq9574 entry.
>> +    then:
>> +      properties:
>> +        clocks:
>> +          minItems: 6
>> +          maxItems: 6
>> +        clock-names:
>> +          items:
>> +            - const: ahb # AHB clock
>> +            - const: aux # Auxiliary clock
>> +            - const: axi_m # AXI Master clock
>> +            - const: axi_s # AXI Slave clock
>> +            - const: axi_bridge # AXI bridge clock
>> +            - const: rchng
>> +        resets:
>> +          minItems: 8
>> +          maxItems: 8
>> +        reset-names:
>> +          items:
>> +            - const: pipe # PIPE reset
>> +            - const: sticky # Core sticky reset
>> +            - const: axi_m_sticky # AXI master sticky reset
>> +            - const: axi_m # AXI master reset
>> +            - const: axi_s_sticky # AXI slave sticky reset
>> +            - const: axi_s # AXI slave reset
>> +            - const: ahb # AHB reset
>> +            - const: aux # AUX reset
>> +
>>     - if:
>>         properties:
>>           compatible:
>> @@ -790,6 +825,7 @@ allOf:
>>                 enum:
>>                   - qcom,pcie-apq8064
>>                   - qcom,pcie-ipq4019
>> +                - qcom,pcie-ipq5332
>>                   - qcom,pcie-ipq8064
>>                   - qcom,pcie-ipq8064v2
>>                   - qcom,pcie-ipq8074
>> --
>> 2.34.1
>>
>>
>
--
Thanks,
Praveenkumar
Krzysztof Kozlowski Dec. 15, 2023, 8:31 a.m. UTC | #2 
On 14/12/2023 07:28, Praveenkumar I wrote:
> Qualcomm IPQ5332 has single-lane and dual-lane PCIe UNIPHY
> with Gen 3 support. This UNIPHY is similar to the one found
> on Qualcomm IPQ5018. Hence add the bindings in qcom,uniphy-pcie.
> 
> Clocks and resets are different for IPQ5332. Update the
> bindings to support both IPQ5018 and IPQ5332.
> 
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> ---
> This patch depends on the below series which adds PCIe support in
> Qualcomm IPQ5018
> https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/
> 
>  .../bindings/phy/qcom,uniphy-pcie-28lp.yaml   | 65 +++++++++++++++++--
>  1 file changed, 58 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
> index 6b2574f9532e..205eaec2291e 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
> @@ -20,19 +20,20 @@ properties:
>      maxItems: 1
>  
>    clocks:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 4
>  
>    clock-names:
> -    items:
> -      - const: pipe_clk
> +    minItems: 1
> +    maxItems: 4
>  
>    resets:
> -    maxItems: 2
> +    minItems: 2
> +    maxItems: 3
>  
>    reset-names:
> -    items:
> -      - const: phy
> -      - const: phy_phy
> +    minItems: 2
> +    maxItems: 3
>  
>    "#phy-cells":
>      const: 0
> @@ -54,6 +55,56 @@ required:
>    - "#clock-cells"
>    - clock-output-names
>  
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,ipq5018-uniphy-pcie-gen2x1
> +              - qcom,ipq5018-uniphy-pcie-gen2x2
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 1

Drop

> +          maxItems: 1
> +        clock-names:
> +          items:
> +            - const: pipe_clk
> +        resets:
> +          minItems: 2

Drop

> +          maxItems: 2
> +        reset-name:

Typo

> +          items:
> +            - const: phy
> +            - const: phy_phy
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,ipq5332-uniphy-pcie-gen3x1
> +              - qcom,ipq5332-uniphy-pcie-gen3x2

There are no such compatibles.

> +    then:
> +      properties:
> +        clocks:
> +          minItems: 4
> +          maxItems: 4
> +        clock-names:
> +          items:
> +            - const: pipe
> +            - const: lane_m
> +            - const: lane_s
> +            - const: phy_ahb
> +        resets:
> +          minItems: 2
> +          maxItems: 2

So where are three items?


> +        reset-name:

Typo

This patch is so confusing, it looks like it does not make any sense.

Best regards,
Krzysztof
Krzysztof Kozlowski Dec. 15, 2023, 8:35 a.m. UTC | #3 
On 14/12/2023 07:28, Praveenkumar I wrote:
> Add support for the PCIe controller on the Qualcomm
> IPQ5332 SoC to the bindings.
> 
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> ---
>  .../devicetree/bindings/pci/qcom,pcie.yaml    | 36 +++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index eadba38171e1..af5e67d2a984 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -21,6 +21,7 @@ properties:
>            - qcom,pcie-apq8064
>            - qcom,pcie-apq8084
>            - qcom,pcie-ipq4019
> +          - qcom,pcie-ipq5332
>            - qcom,pcie-ipq6018
>            - qcom,pcie-ipq8064
>            - qcom,pcie-ipq8064-v2
> @@ -170,6 +171,7 @@ allOf:
>          compatible:
>            contains:
>              enum:
> +              - qcom,pcie-ipq5332
>                - qcom,pcie-ipq6018
>                - qcom,pcie-ipq8074-gen3
>      then:
> @@ -332,6 +334,39 @@ allOf:
>              - const: ahb # AHB reset
>              - const: phy_ahb # PHY AHB reset
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,pcie-ipq5332
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 6
> +          maxItems: 6
> +        clock-names:
> +          items:
> +            - const: ahb # AHB clock
> +            - const: aux # Auxiliary clock
> +            - const: axi_m # AXI Master clock
> +            - const: axi_s # AXI Slave clock
> +            - const: axi_bridge # AXI bridge clock
> +            - const: rchng
> +        resets:
> +          minItems: 8
> +          maxItems: 8
> +        reset-names:
> +          items:
> +            - const: pipe # PIPE reset

No sleep reset? Otherwise it looks like some existing entry, so you
should use the same order of resets.



Best regards,
Krzysztof