Message ID | 20231211162331.435900-1-peter.griffin@linaro.org |
---|---|
Headers | show |
Series | Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board | expand |
On 11/12/2023 20:46, Peter Griffin wrote: >>> +#include <linux/platform_device.h> > > You are correct, this header isn't required. If a new series is > required I will remove it. I dropped it while applying. > > Whilst you're here I'd like to draw your attention to [PATCH 2/16] > where I've removed your reviewed-by tag in v7 because I added the ect > node documentation in google.yaml. The empty ect node is required to > be present by the bootloader or the device will boot loop. Can you > re-review that patch? > > The alternative is to remove the empty ect node, and the binding > documentation for it and add your Reviewed-by tag back again. But then > an upstream kernel won't boot 'out the box' on a pixel 6 which seems > less than ideal default behaviour. Best regards, Krzysztof
On Mon, 11 Dec 2023 16:23:18 +0000, Peter Griffin wrote: > Add dedicated google-gs101-uart compatible to the dt-schema for > representing uart of the Google Tensor gs101 SoC. > > Applied, thanks! [03/16] dt-bindings: serial: samsung: Add google-gs101-uart compatible https://git.kernel.org/krzk/linux/c/bad3bc0a23b74e7b353978b6f58eed6c0f3b51a0 Best regards,
On Mon, 11 Dec 2023 16:23:22 +0000, Peter Griffin wrote: > These plls are found in the Tensor gs101 SoC found in the Pixel 6. > > pll0516x: Integer PLL with high frequency > pll0517x: Integer PLL with middle frequency > pll0518x: Integer PLL with low frequency > > PLL0516x > FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV) > > [...] Applied, thanks! [07/16] clk: samsung: clk-pll: Add support for pll_{0516,0517,518} https://git.kernel.org/krzk/linux/c/13ff3bdafdd569e62e59330de18aae25ec15c97b Best regards,
On Tue, 12 Dec 2023 at 19:38, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 11/12/2023 20:46, Peter Griffin wrote: > >>> +#include <linux/platform_device.h> > > > > You are correct, this header isn't required. If a new series is > > required I will remove it. > > I dropped it while applying. Thanks Krzysztof :)
On 12/11/23 08:23, Peter Griffin wrote: > This patch adds the compatibles and drvdata for the Google > gs101 SoC found in Pixel 6, Pixel 6a & Pixel 6 pro phones. > > Similar to Exynos850 it has two watchdog instances, one for > each cluster and has some control bits in PMU registers. > > gs101 also has the dbgack_mask bit in wtcon register, so > we also enable QUIRK_HAS_DBGACK_BIT. > > Tested-by: Will McVicker <willmcvicker@google.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > drivers/watchdog/s3c2410_wdt.c | 49 ++++++++++++++++++++++++++++++---- > 1 file changed, 44 insertions(+), 5 deletions(-) > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > index b7a03668f743..c3046610ab5d 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -69,6 +69,13 @@ > #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25 > #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24 > > +#define GS_CLUSTER0_NONCPU_OUT 0x1220 > +#define GS_CLUSTER1_NONCPU_OUT 0x1420 > +#define GS_CLUSTER0_NONCPU_INT_EN 0x1244 > +#define GS_CLUSTER1_NONCPU_INT_EN 0x1444 > +#define GS_CLUSTER2_NONCPU_INT_EN 0x1644 > +#define GS_RST_STAT_REG_OFFSET 0x3B44 > + > /** > * DOC: Quirk flags for different Samsung watchdog IP-cores > * > @@ -270,7 +277,35 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = { > QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, > }; > > +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = { > + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN, > + .mask_bit = 2, > + .mask_reset_inv = true, > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > + .rst_stat_bit = 0, > + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT, > + .cnt_en_bit = 8, > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | > + QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG | > + QUIRK_HAS_DBGACK_BIT, > +}; > + > +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = { > + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN, > + .mask_bit = 2, > + .mask_reset_inv = true, > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > + .rst_stat_bit = 1, > + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT, > + .cnt_en_bit = 7, > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | > + QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG | > + QUIRK_HAS_DBGACK_BIT, > +}; > + > static const struct of_device_id s3c2410_wdt_match[] = { > + { .compatible = "google,gs101-wdt", > + .data = &drv_data_gs101_cl0 }, > { .compatible = "samsung,s3c2410-wdt", > .data = &drv_data_s3c2410 }, > { .compatible = "samsung,s3c6410-wdt", > @@ -605,9 +640,10 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) > } > > #ifdef CONFIG_OF > - /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */ > + /* Choose Exynos9 SoC family driver data w.r.t. cluster index */ > if (variant == &drv_data_exynos850_cl0 || > - variant == &drv_data_exynosautov9_cl0) { > + variant == &drv_data_exynosautov9_cl0 || > + variant == &drv_data_gs101_cl0) { > u32 index; > int err; > > @@ -620,9 +656,12 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) > case 0: > break; > case 1: > - variant = (variant == &drv_data_exynos850_cl0) ? > - &drv_data_exynos850_cl1 : > - &drv_data_exynosautov9_cl1; > + if (variant == &drv_data_exynos850_cl0) > + variant = &drv_data_exynos850_cl1; > + else if (variant == &drv_data_exynosautov9_cl0) > + variant = &drv_data_exynosautov9_cl1; > + else if (variant == &drv_data_gs101_cl0) > + variant = &drv_data_gs101_cl1; > break; > default: > return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);